Skip spill coalescing when payload is address taken

When payload of spill intrinsic is address taken, we cannot simply
replace the virtual register with a temporary coalesced range. That's
because address takens can have indirect def.

Treat such cases as non-spill coalesceable.

This is a functional fix.

Author: pratikashar

visa/SpillCleanup.cpp

@@ -1070,7 +1070,8 @@ void CoalesceSpillFills::spills() {
           spillsToCoalesce.clear();
         }
 
-        if (isGRFAssigned(inst->asSpillIntrinsic()->getPayload())) {
+        if (isGRFAssigned(inst->asSpillIntrinsic()->getPayload()) ||
+            inst->asSpillIntrinsic()->getPayload()->getTopDcl()->isAddrSpillFill()) {
           if (spillsToCoalesce.size() == 0) {
             ++instIter;
             continue;