Avoid hard-coding SIMD size for render target write with stencil

Change-Id: I339bfad6fbd8362ac7628589169f5c86625aa74f

Author: weiyu-chen

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -4180,7 +4180,7 @@ bool EmitPass::interceptRenderTargetWritePayloadCoalescing(
     //Stencil is only supported in SIMD8 mode
     if (inst->hasStencil())
     {
-        IGC_ASSERT(m_currShader->m_SIMDSize == SIMDMode::SIMD8);
+        IGC_ASSERT(m_currShader->m_Platform->supportsStencil(m_currShader->m_SIMDSize));
         IGC_ASSERT(vStencilOpnd == nullptr);
 
         CVariable* temp = m_currShader->GetNewAlias(rootPayloadVar, ISA_TYPE_UB, (uint16_t)offset, 0);
@@ -4194,6 +4194,7 @@ bool EmitPass::interceptRenderTargetWritePayloadCoalescing(
             m_encoder->SetSrcRegion(0, 32, 8, 4);
         }
         m_currShader->CopyVariable(temp, ubSrc, 0);
+
         vStencilOpnd = temp;
     }
     return true;
@@ -4300,7 +4301,6 @@ void EmitPass::prepareRenderTargetWritePayload(
         }
     }
 
-    //Stencil is only supported in SIMD8 mode
     if (inst->hasStencil())
     {
         varStencilOpnd = GetSymbol(inst->getStencil());

IGC/Compiler/CISACodeGen/PayloadMapping.cpp

@@ -206,9 +206,8 @@ int PayloadMapping::GetRightReservedOffset_RTWrite(const Instruction* inst, SIMD
 
     if (rtwi->hasStencil())
     {
-        //Must not be set in simd16 mode.
-        IGC_ASSERT(simdMode == SIMDMode::SIMD8);
-        offset += 32; //256bits=1grf
+        IGC_ASSERT(m_CodeGenContext->platform.supportsStencil(simdMode));
+        offset += m_CodeGenContext->platform.getGRFSize();
     }
 
     if (rtwi->hasDepth())

IGC/Compiler/CISACodeGen/PixelShaderCodeGen.cpp

@@ -1118,7 +1118,7 @@ namespace IGC
             return false;
         }
 
-        if (m_HasoStencil && simdMode != SIMDMode::SIMD8)
+        if (m_HasoStencil && !ctx->platform.supportsStencil(simdMode))
         {
             return false;
         }

IGC/Compiler/CISACodeGen/Platform.hpp

@@ -294,6 +294,11 @@ namespace IGC
         return m_platformInfo.eRenderCoreFamily <= IGFX_GEN11_CORE;
     }
 
+    bool supportsStencil(SIMDMode simdMode) const
+    {
+        return getMinDispatchMode() == SIMDMode::SIMD16 ? true : simdMode == SIMDMode::SIMD8;
+    }
+
     bool supportsSIMD16TypedRW() const
     {
         return false;