Minor refactor

Minor refactor

Author: skarczew

IGC/Compiler/CISACodeGen/ShaderCodeGen.hpp

@@ -137,7 +137,9 @@ class CShader
 
     // if true, HW will pass one GRF NOS of inlinedata to payload, (compute only right now)
     virtual bool passNOSInlineData() { return false; }
-    virtual bool loadThreadPayload() { return false; }
+    virtual bool loadThreadPayload() {
+            return false;
+    }
     virtual int getAnnotatedNumThreads() { return -1; }
     virtual bool IsRegularGRFRequested() { return false; }
     virtual bool IsLargeGRFRequested() { return false; }

visa/PrologEpilog.cpp

@@ -363,7 +363,6 @@ class PayloadLoader
         AlignUp(k.getInt32KernelAttr(Attributes::ATTR_PerThreadInputSize),
                 k.numEltPerGRF<Type_UB>()) / k.numEltPerGRF<Type_UB>())
   {
-
     auto rtmpRegNum = k.getNumRegTotal() - 1;
     rtmp = b.createHardwiredDeclare(k.numEltPerGRF<Type_UD>(), Type_UD, rtmpRegNum, 0);