Do not split dead parts of IEEE intrinsics

These intrinsics end up as DIVM and SQRTM visa instructions and their
execution size is restored to 8 or 16 by finalizer, so there is no sense
in splitting their unused parts

(cherry picked from commit 82e2902)

Author: mshelego

IGC/VectorCompiler/lib/GenXCodeGen/GenXLegalization.cpp

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2017-2023 Intel Corporation
+Copyright (C) 2017-2024 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -1124,10 +1124,20 @@ unsigned GenXLegalization::splitDeadElements(unsigned Width,
   auto *V = getExecWidthValue();
   auto *ElemTy = V->getType()->getScalarType();
   // The most math instructions require exec size to be 8 or 16 in case of half
-  // float. Even if we reduce the width here, it will be very likely set back to
-  // the 'native' width by finalizer
+  // float. And some of them require it even for other float types. Even if we
+  // reduce the width here, it will be very likely set back to the 'native'
+  // width by finalizer
   if (ElemTy->isHalfTy())
     return Width;
+  if (ElemTy->isFloatTy()) {
+    auto Main = B.getMainInst();
+    if (Main) {
+      unsigned IID = vc::getAnyIntrinsicID(Main->Inst);
+      if (IID == GenXIntrinsic::genx_ieee_div ||
+          IID == GenXIntrinsic::genx_ieee_sqrt)
+        return Width;
+    }
+  }
   const auto &LiveElems = LE->getLiveElements(V);
   if (LiveElems.size() > 1 || LiveElems.isAllDead() || !LiveElems.isAnyDead())
     return Width;

IGC/VectorCompiler/test/Legalization/live-elements.ll

@@ -1,13 +1,16 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023 Intel Corporation
+; Copyright (C) 2023-2024 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
 ;============================ end_copyright_notice =============================
 
 ; RUN: %opt %use_old_pass_manager% -GenXLegalization -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s
 
+declare <16 x float> @llvm.genx.ieee.sqrt.v16f32(<16 x float>)
+declare <16 x float> @llvm.genx.ieee.div.v16f32(<16 x float>, <16 x float>)
+
 ; NO SPLIT
 ; CHECK-LABEL: @test1
 ; CHECK: add <16 x i32>
@@ -153,3 +156,14 @@ define <16 x i16> @test15(<16 x half> %arg) {
   ret <16 x i16> %and
 }
 
+; NO SPLIT FOR IEEE INTRINSICS
+; CHECK-LABEL: @test16
+; CHECK:       call <16 x float> @llvm.genx.ieee.sqrt.v16f32
+; CHECK-NEXT:  call <16 x float> @llvm.genx.ieee.div.v16f32
+define <16 x i16> @test16(<16 x float> %arg) {
+  %sqrt = call <16 x float> @llvm.genx.ieee.sqrt.v16f32(<16 x float> %arg)
+  %div = call <16 x float> @llvm.genx.ieee.div.v16f32(<16 x float> %arg, <16 x float> %sqrt)
+  %int = fptoui <16 x float> %div to <16 x i16>
+  %and = and <16 x i16> %int, <i16 1, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+  ret <16 x i16> %and
+}