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Commit 1734d78

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fangliu2020igcbot
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Add a reserved vISA opcode
Add a reserved vISA opcode
1 parent e3a0d4c commit 1734d78

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4 files changed

+18
-3
lines changed

4 files changed

+18
-3
lines changed

visa/G4_IR.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3170,7 +3170,8 @@ static void emitPredWrEn(std::ostream &output, G4_INST &inst) {
31703170

31713171
static void emitExecSize(std::ostream &output, const G4_INST &inst) {
31723172
auto execSize = static_cast<int>(inst.getExecSize());
3173-
if (inst.opcode() != G4_nop && inst.opcode() != G4_wait) {
3173+
if (inst.opcode() != G4_nop &&
3174+
inst.opcode() != G4_wait) {
31743175
output << '(';
31753176
if (execSize == UNDEFINED_EXEC_SIZE) {
31763177
output << "??";

visa/IsaDescription.cpp

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,8 @@ struct ISA_Inst_Info ISA_Inst_Table[ISA_OPCODE_ENUM_SIZE] = {
177177
{ISA_RESERVED_99, ISA_Inst_Reserved, "reserved99", 0, 0},
178178
{ISA_RESERVED_9A, ISA_Inst_Reserved, "reserved9a", 0, 0},
179179
{ISA_INVM, ISA_Inst_Arith, "invm", 2, 2},
180-
{ISA_RSQTM, ISA_Inst_Arith, "rsqtm", 1, 2}
180+
{ISA_RSQTM, ISA_Inst_Arith, "rsqtm", 1, 2},
181+
{ISA_RESERVED_9D, ISA_Inst_Reserved, "reserved9d", 0, 0}
181182
};
182183

183184
VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
@@ -2816,6 +2817,17 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
28162817
},
28172818

28182819
},
2820+
2821+
// 157 (0x9D)
2822+
{
2823+
ALL,
2824+
ISA_RESERVED_9D,
2825+
ISA_Inst_Reserved,
2826+
"reserved_9d",
2827+
0,
2828+
0,
2829+
{},
2830+
},
28192831
};
28202832

28212833
static const ISA_SubInst_Desc VASubOpcodeDesc[] = {

visa/LocalScheduler/Dependencies_G4IR.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,8 @@ DepType vISA::CheckBarrier(G4_INST *inst) {
206206
inst->getMsgDesc()->getSFID() == SFID::SPAWNER) {
207207
return MSG_BARRIER;
208208
}
209-
} else if (inst->opcode() == G4_wait || inst->isYieldInst()) {
209+
} else if (inst->opcode() == G4_wait ||
210+
inst->isYieldInst()) {
210211
return MSG_BARRIER;
211212
} else if (inst->isFlowControl()) {
212213
// All control flow instructions are scheduling barriers

visa/include/visa_igc_common_header.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -420,6 +420,7 @@ typedef enum {
420420
ISA_RESERVED_9A = 0x9A,
421421
ISA_INVM = 0x9B,
422422
ISA_RSQTM = 0x9C,
423+
ISA_RESERVED_9D = 0x9D,
423424
ISA_NUM_OPCODE,
424425
ISA_OPCODE_ENUM_SIZE = 0xFF
425426
} ISA_Opcode;

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