Changes in code.

Change-Id: I997556c6f8f5fb1efbe903d419fdc4af68688f83

Author: Dimus77

visa/CMakeLists.txt

@@ -188,7 +188,6 @@ set(GenX_Common_Sources_External
   SpillCleanup.cpp
   Rematerialization.cpp
   RPE.cpp
-  VarSplit.cpp
   ${LocalScheduler_SOURCES}
 )
 
@@ -265,7 +264,6 @@ set(GenX_Common_Headers
   Metadata.h
   RPE.h
   include/gtpin_IGC_interface.h
-  VarSplit.h
   ${LocalScheduler_HEADERS}
 )
 set(GenX_CISA_dis_Common_Headers

visa/Gen4_IR.hpp

@@ -700,7 +700,6 @@ class G4_INST
     G4_SpillIntrinsic* asSpillIntrinsic() const;
     bool isFillIntrinsic() const;
     G4_FillIntrinsic* asFillIntrinsic() const;
-    bool isSplitIntrinsic() const;
     bool isLifeTimeEnd() const { return op == G4_pseudo_lifetime_end; }
     bool isMov() const { return G4_Inst_Table[op].instType == InstTypeMov; }
     bool isLogic() const { return G4_Inst_Table[op].instType == InstTypeLogic; }
@@ -1432,7 +1431,6 @@ enum class Intrinsic
     PseudoKill,
     Spill,
     Fill,
-    Split,
     NumIntrinsics
 };
 
@@ -1470,8 +1468,7 @@ static const IntrinsicInfo G4_Intrinsics[(int)Intrinsic::NumIntrinsics] =
     {Intrinsic::MemFence,   "mem_fence",    0,      0,      Phase::BinaryEncoding,  { 0, 0, 0, false, false } },
     {Intrinsic::PseudoKill, "pseudo_kill",  1,      1,      Phase::RA,              { 0, 0, 0, false, false} },
     {Intrinsic::Spill,      "spill",        1,      2,      Phase::RA,              { 0, 0, 0, false, false } },
-    {Intrinsic::Fill,       "fill",         1,      1,      Phase::RA,              { 0, 0, 0, false, false } },
-    {Intrinsic::Split,      "split",        1,      1,      Phase::RA,              { 0, 0, 0, false, false } },
+    {Intrinsic::Fill,       "fill",         1,      1,      Phase::RA,              { 0, 0, 0, false, false } }
 };
 
 namespace vISA
@@ -3823,11 +3820,6 @@ inline G4_FillIntrinsic* G4_INST::asFillIntrinsic() const
     return const_cast<G4_FillIntrinsic*>(reinterpret_cast<const G4_FillIntrinsic*>(this));
 }
 
-inline bool G4_INST::isSplitIntrinsic() const
-{
-    return isIntrinsic() && asIntrinsicInst()->getIntrinsicId() == Intrinsic::Split;
-}
-
 inline const char* G4_INST::getLabelStr() const
 {
     MUST_BE_TRUE(srcs[0] != NULL && srcs[0]->isLabel(), ERROR_UNKNOWN);

visa/GraphColor.cpp

@@ -5544,42 +5544,17 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF, bool doBankConfl
         doBankConflict, availableGregs, availableSubRegs, availableAddrs, availableFlags, weakEdgeUsage);
     bool noIndirForceSpills = builder.getOption(vISA_NoIndirectForceSpills);
 
-    auto& varSplitPass = *gra.getVarSplitPass();
-
-    auto assignColor = [&](LiveRange* lr)
+    // colorOrder is in reverse order (unconstrained at front)
+    for (auto iter = colorOrder.rbegin(), iterEnd = colorOrder.rend(); iter != iterEnd; ++iter)
     {
+        LiveRange* lr = *iter;
         auto lrVar = lr->getVar();
 
         //
-        // assign register to live ranges
+        // assign regiser to live ranges
         //
         if (lr->getPhyReg() == NULL && !lrVar->isSpilled() && !lr->getIsPartialDcl()) // no assigned register yet and not spilled
         {
-            G4_Declare* parentDcl = nullptr;
-            bool skipParentIntf = false;
-            if (lr->hasAllocHint())
-            {
-                parms.startGRFReg = lr->getAllocHint();
-                if (varSplitPass.isPartialDcl(lr->getDcl()))
-                {
-                    parentDcl = varSplitPass.getParentDcl(lr->getDcl());
-                    auto parentGRF = parentDcl->getRegVar()->getPhyReg();
-                    if (!parentGRF && parentDcl->getRegVar()->isRegAllocPartaker())
-                    {
-                        parentGRF = lrs[parentDcl->getRegVar()->getId()]->getPhyReg();
-                    }
-                    if (parentGRF)
-                    {
-                        auto siblingNum = varSplitPass.getSiblingNum(lr->getDcl());
-                        auto parentGRFNum = parentGRF->asGreg()->getRegNum();
-                        auto forbiddenStart = parentGRFNum + ((siblingNum + 1) * lr->getDcl()->getNumRows());
-                        auto forbiddenEnd = parentGRFNum + parentDcl->getNumRows();
-                        lr->markForbidden(forbiddenStart, forbiddenEnd - forbiddenStart);
-                        skipParentIntf = true;
-                    }
-                }
-            }
-
             unsigned lr_id = lrVar->getId();
             //
             // compute what registers are already assigned
@@ -5588,6 +5563,7 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF, bool doBankConfl
 
             std::vector<unsigned int>& intfs = intf.getSparseIntfForVar(lr_id);
             auto weakEdgeSet = intf.getCompatibleSparseIntf(lrVar->getDeclare()->getRootDeclare());
+
             for (auto it : intfs)
             {
                 LiveRange* lrTemp = lrs[it];
@@ -5598,9 +5574,6 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF, bool doBankConfl
                         continue;
                     }
 
-                    if (skipParentIntf && lrTemp->getDcl() == parentDcl)
-                        continue;
-
                     regUsage.updateRegUsage(lrTemp);
                 }
             }
@@ -5656,6 +5629,7 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF, bool doBankConfl
 
             ColorHeuristic heuristic = colorHeuristicGRF;
 
+
             bool failed_alloc = false;
             G4_Declare* dcl = lrVar->getDeclare();
 
@@ -5680,7 +5654,7 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF, bool doBankConfl
                 // When evenAlignNeeded is true, it is binding for correctness
                 bool evenAlignNeeded = gra.isEvenAligned(lrVar->getDeclare());
                 BankAlign align = evenAlignNeeded ? BankAlign::Even : BankAlign::Either;
-                if (allocFromBanks && !lr->hasAllocHint())
+                if (allocFromBanks)
                 {
 
                     if (!isHybrid && oneGRFBankDivision &&
@@ -5694,8 +5668,7 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF, bool doBankConfl
                 else
                 {
                     failed_alloc |= !regUsage.assignRegs(highInternalConflict, lr, lr->getForbidden(),
-                        align, gra.getSubRegAlign(lrVar->getDeclare()), heuristic, lr->getSpillCost(),
-                        lr->hasAllocHint());
+                        align, gra.getSubRegAlign(lrVar->getDeclare()), heuristic, lr->getSpillCost());
                 }
             }
 
@@ -5723,52 +5696,11 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF, bool doBankConfl
                     spilledLRs.push_back(lr);
                 }
             }
-            else
-            {
-                // Allocation succeeded, set hint if this is a split/child dcl
-                if (varSplitPass.isSplitDcl(dcl) || varSplitPass.isPartialDcl(dcl))
-                {
-                    varSplitPass.writeHints(dcl, lrs);
-                }
-            }
         }
 #ifdef DEBUG_VERBOSE_ON
         lr->dump();
         COUT_ERROR << std::endl;
 #endif
-        return true;
-    };
-
-    // colorOrder is in reverse order (unconstrained at front)
-    for (auto iter = colorOrder.rbegin(), iterEnd = colorOrder.rend(); iter != iterEnd; ++iter)
-    {
-        auto lr = (*iter);
-        bool ret = assignColor(lr);
-
-        // early exit
-        if (!ret)
-            return false;
-
-        if (gra.getIterNo() == 0)
-        {
-            if(varSplitPass.isSplitDcl(lr->getDcl()))
-            {
-                // Try allocating children, out of order in hopes
-                // of getting a coalescable assignment
-                auto children = varSplitPass.getChildren(lr->getDcl());
-                for (auto child : *children)
-                {
-                    if (child->getRegVar()->isRegAllocPartaker())
-                    {
-                        auto childLR = lrs[child->getRegVar()->getId()];
-                        if (!childLR->getPhyReg())
-                        {
-                            assignColor(childLR);
-                        }
-                    }
-                }
-            }
-        }
     }
 
     // record RA type
@@ -8934,7 +8866,6 @@ int GlobalRA::coloringRegAlloc()
         {
             std::cout << "--GRF RA iteration " << iterationNo << "--\n";
         }
-        setIterNo(iterationNo);
 
         resetGlobalRAStates();
 

visa/GraphColor.h

@@ -34,8 +34,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include <unordered_set>
 #include <limits>
 #include "RPE.h"
+
 #include "BitSet.h"
-#include "VarSplit.h"
 
 #define BITS_DWORD 32
 #define SCRATCH_MSG_LIMIT (128 * 1024)
@@ -91,8 +91,6 @@ class LiveRange
     AssignedReg reg;
     float spillCost;
     BankConflict bc = BankConflict::BANK_CONFLICT_NONE;
-    const static unsigned int UndefHint = 0xffffffff;
-    unsigned int allocHint = UndefHint;
 
     union {
         uint16_t bunch = 0;
@@ -188,10 +186,6 @@ class LiveRange
     void setParentLRID(int id) { parentLRID = id; }
     unsigned getParentLRID() const { return parentLRID; }
 
-    unsigned int getAllocHint() const { return allocHint; }
-    bool hasAllocHint() const { return allocHint != UndefHint; }
-    void setAllocHint(unsigned int h) { allocHint = h; }
-
     // From VarBasis
     public:
         void allocForbidden(vISA::Mem_Manager& mem, bool reserveStackCallRegs, unsigned reserveSpillSize, unsigned rerservedRegNum);
@@ -751,9 +745,6 @@ namespace vISA
         // new temps for each reference of spilled address/flag decls
         std::unordered_set<G4_Declare*> addrFlagSpillDcls;
 
-        // store iteration number for GRA loop
-        unsigned int iterNo = 0;
-
         void expandFillNonStackcall(uint32_t& numRows, uint32_t& offset, short& rowOffset, G4_SrcRegRegion* header, G4_DstRegRegion* resultRgn, G4_BB* bb, INST_LIST_ITER& instIt);
         void expandSpillNonStackcall(uint32_t& numRows, uint32_t& offset, short& rowOffset, G4_SrcRegRegion* header, G4_SrcRegRegion* payload, G4_BB* bb, INST_LIST_ITER& instIt);
         void expandFillStackcall(uint32_t& numRows, uint32_t& offset, short& rowOffset, G4_SrcRegRegion* header, G4_DstRegRegion* resultRgn, G4_BB* bb, INST_LIST_ITER& instIt);
@@ -765,10 +756,6 @@ namespace vISA
         PhyRegPool& regPool;
         PointsToAnalysis& pointsToAnalysis;
         FCALL_RET_MAP fcallRetMap;
-        VarSplitPass* splitPass = nullptr;
-
-        void setVarSplitPass(VarSplitPass* p) { splitPass = p; }
-        VarSplitPass* getVarSplitPass() { return splitPass; }
 
         unsigned int getSubRetLoc(G4_BB* bb)
         {
@@ -786,8 +773,6 @@ namespace vISA
         void insertCallReturnVar();
         void insertSaveAddr(G4_BB*);
         void insertRestoreAddr(G4_BB*);
-        void setIterNo(unsigned int i) { iterNo = i; }
-        unsigned int getIterNo() { return iterNo; }
 
         G4_Declare* getRetDecl(uint32_t retLoc)
         {