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jgu222Zuul
jgu222
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Zuul
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Use !isAllLanActive() to replace isInSimdFlow().
isAllLaneActive() uses isDivergent() info instead of the existing isInSimdFlow. Once this is done. isInSimdFlow can be removed. Change-Id: I61f7c41bd0db5802a32dab722af75b40470e8916
1 parent babf96c commit 22c98c4

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10 files changed

+33
-33
lines changed

10 files changed

+33
-33
lines changed

‎visa/FlowGraph.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5922,9 +5922,9 @@ void G4_BB::print(std::ostream& OS) const
59225922
{
59235923
OS << " [" << getBBTypeStr() << "], ";
59245924
}
5925-
if (isInSimdFlow())
5925+
if (isDivergent())
59265926
{
5927-
OS << " [inSimdFlow],";
5927+
OS << " [inDivergent],";
59285928
}
59295929
OS << " Pred: ";
59305930
for (auto pred : Preds)

‎visa/GraphColor.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6195,7 +6195,7 @@ bool GlobalRA::shouldPreloadDst(
61956195

61966196
if (isPartialRegion(spilledRangeRegion, execSize) ||
61976197
isUnalignedRegion(spilledRangeRegion, execSize) ||
6198-
instContext->isPartialWriteForSpill(curBB->isInSimdFlow())) {
6198+
instContext->isPartialWriteForSpill(!curBB->isAllLaneActive())) {
61996199
return true;
62006200
}
62016201
// No pre-load for whole and aligned region writes

‎visa/LVN.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ bool LVN::canReplaceUses(INST_LIST_ITER inst_it, UseList& uses, G4_INST* lvnInst
221221
break;
222222
}
223223

224-
if (bb->isInSimdFlow())
224+
if (!bb->isAllLaneActive())
225225
{
226226
auto defCoversUseEmask = defInst->getMaskOffset() <= useInst->getMaskOffset() &&
227227
(defInst->getMaskOffset() + defInst->getExecSize() >= useInst->getMaskOffset() + useInst->getExecSize());
@@ -921,7 +921,7 @@ bool LVN::opndsMatch(T* opnd1, K* opnd2)
921921
G4_INST* inst1 = opnd1->getInst();
922922
G4_INST* inst2 = opnd2->getInst();
923923
// Compare emask for opnd1, opnd2 instructions
924-
if (bb->isInSimdFlow())
924+
if (!bb->isAllLaneActive())
925925
{
926926
if (inst1->isWriteEnableInst() != inst2->isWriteEnableInst())
927927
{
@@ -1233,7 +1233,7 @@ bool LVN::valuesMatch(Value& val1, Value& val2)
12331233
match = false;
12341234
}
12351235

1236-
if (match && bb->isInSimdFlow())
1236+
if (match && !bb->isAllLaneActive())
12371237
{
12381238
G4_INST* val1Inst = val1.getInst();
12391239
G4_INST* val2Inst = val2.getInst();

‎visa/LocalDataflow.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -472,7 +472,7 @@ static void processWriteOpnds(G4_BB *BB, G4_INST *Inst, LocalLivenessInfo &LLI)
472472
void FlowGraph::localDataFlowAnalysis()
473473
{
474474
for (auto BB : BBs) {
475-
LocalLivenessInfo LLI(BB->isInSimdFlow());
475+
LocalLivenessInfo LLI(!BB->isAllLaneActive());
476476
for (auto I = BB->rbegin(), E = BB->rend(); I != E; ++I) {
477477
G4_INST* Inst = *I;
478478
G4_opcode Op = Inst->opcode();

‎visa/Optimizer.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1844,7 +1844,7 @@ static bool canHoist(FlowGraph &fg, G4_BB *bb, INST_LIST_RITER revIter)
18441844
// Cannot hoist if this is not a move, or it is a global operand.
18451845
if (inst->opcode() != G4_mov ||
18461846
fg.globalOpndHT.isOpndGlobal(inst->getSrc(0)) ||
1847-
!inst->canHoist(bb->isInSimdFlow(), fg.builder->getOptions()))
1847+
!inst->canHoist(!bb->isAllLaneActive(), fg.builder->getOptions()))
18481848
{
18491849
return false;
18501850
}
@@ -1864,7 +1864,7 @@ static bool canHoist(FlowGraph &fg, G4_BB *bb, INST_LIST_RITER revIter)
18641864
for (auto I = inst->def_begin(), E = inst->def_end(); I != E; ++I)
18651865
{
18661866
ASSERT_USER(I->second == Opnd_src0, "invalid use-def chain");
1867-
if (!inst->canHoistTo(I->first, bb->isInSimdFlow()))
1867+
if (!inst->canHoistTo(I->first, !bb->isAllLaneActive()))
18681868
return false;
18691869

18701870
auto defInst = I->first;
@@ -2152,7 +2152,7 @@ static void doHoisting(FlowGraph &fg, G4_BB *bb, INST_LIST_RITER revIter)
21522152
defInst->setExecSize(defInst->getExecSize() * inst->getExecSize());
21532153
}
21542154
defInst->setSaturate(inst->getSaturate() || defInst->getSaturate());
2155-
if (bb->isInSimdFlow())
2155+
if (!bb->isAllLaneActive())
21562156
{
21572157
// set writeEnable of dstInst to be off
21582158
defInst->setOptions((defInst->getOption() & ~0xFFF000C) |
@@ -2832,7 +2832,7 @@ void Optimizer::newLocalCopyPropagation()
28322832
break;
28332833
}
28342834

2835-
if (!inst->canPropagateTo(useInst, opndNum, MT, bb->isInSimdFlow()))
2835+
if (!inst->canPropagateTo(useInst, opndNum, MT, !bb->isAllLaneActive()))
28362836
{
28372837
canRemove = false;
28382838
break;
@@ -3645,7 +3645,7 @@ bool Optimizer::createSmov(G4_BB *bb, G4_INST* flagMove, G4_INST* next_inst)
36453645
return false;
36463646
}
36473647

3648-
if (builder.getOptions()->getTarget() == VISA_3D || bb->isInSimdFlow())
3648+
if (builder.getOptions()->getTarget() == VISA_3D || !bb->isAllLaneActive())
36493649
{
36503650
if (!flagMove->isWriteEnableInst())
36513651
{
@@ -3733,7 +3733,7 @@ bool Optimizer::foldCmpToCondMod(G4_BB* bb, INST_LIST_ITER& iter)
37333733
return false;
37343734
}
37353735

3736-
if (builder.getOptions()->getTarget() == VISA_3D || bb->isInSimdFlow())
3736+
if (builder.getOptions()->getTarget() == VISA_3D || !bb->isAllLaneActive())
37373737
{
37383738
// Make sure masks of both instructions are same
37393739
if (inst->getMaskOption() != cmpInst->getMaskOption())
@@ -8690,7 +8690,7 @@ void genBucket(G4_INST *send, Bucket *bucket, RW rwType) {
86908690
inst->getPredicate() ||
86918691
Seen.count(inst) > 0 ||
86928692
inst->def_size() != 1 ||
8693-
!inst->canHoist(bb->isInSimdFlow(), fg.builder->getOptions()) )
8693+
!inst->canHoist(!bb->isAllLaneActive(), fg.builder->getOptions()) )
86948694
{
86958695
ii++;
86968696
continue;
@@ -8781,7 +8781,7 @@ void genBucket(G4_INST *send, Bucket *bucket, RW rwType) {
87818781
(!(inst->isWriteEnableInst()) &&
87828782
useInst->getMaskOption() != instMaskOption) ||
87838783
//fix described above
8784-
(bb->isInSimdFlow() &&
8784+
(!bb->isAllLaneActive() &&
87858785
!inst->isWriteEnableInst() &&
87868786
!(inst->getExecSize() == defInst->getExecSize() &&
87878787
inst->getExecSize() == useInst->getExecSize())
@@ -9852,10 +9852,10 @@ void Optimizer::mergeScalarInst()
98529852
G4_INST *inst = *ii;
98539853
auto nextIter = ii;
98549854
++nextIter;
9855-
if (nextIter != iiEnd && isMergeCandidate(inst, builder, bb->isInSimdFlow()))
9855+
if (nextIter != iiEnd && isMergeCandidate(inst, builder, !bb->isAllLaneActive()))
98569856
{
98579857
BUNDLE_INFO* bundle = new (mergeManager) BUNDLE_INFO(bb, ii, bundleSizeLimit);
9858-
findInstructionToMerge(bundle, nextIter, bb->end(), builder, bb->isInSimdFlow());
9858+
findInstructionToMerge(bundle, nextIter, bb->end(), builder, !bb->isAllLaneActive());
98599859
if (bundle->size > 1)
98609860
{
98619861
bundles.push_back(bundle);

‎visa/ReduceExecSize.cpp‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -246,7 +246,7 @@ bool HWConformity::checkSrcCrossGRF( INST_LIST_ITER& iter, G4_BB* bb )
246246
}
247247

248248
auto doSplit = [&](bool canCrossGRF) -> void {
249-
if (inst->usesFlag() || (bb->isInSimdFlow() && !inst->isWriteEnableInst()))
249+
if (inst->usesFlag() || (!bb->isAllLaneActive() && !inst->isWriteEnableInst()))
250250
{
251251
// splitting may be unsafe, insert a move then split the move
252252
G4_Operand* newSrc = insertMovBefore(iter, i, inst->getSrc(i)->getType(), bb);
@@ -384,7 +384,7 @@ bool HWConformity::reduceExecSize( INST_LIST_ITER iter, G4_BB* bb )
384384
bool compOpt = false,
385385
forceEvenSplit = ( execSize == 32 && inst->opcode() == G4_sel && inst->getCondMod() ) || packedByteDst;
386386
uint8_t numInFirstMov = 0;
387-
bool useFlag = inst->getPredicate() || inst->getCondMod() || ( bb->isInSimdFlow() && !inst->isWriteEnableInst() );
387+
bool useFlag = inst->getPredicate() || inst->getCondMod() || ( !bb->isAllLaneActive() && !inst->isWriteEnableInst() );
388388
bool evenSplitDst = false;
389389

390390
// separate the checks for BDW to make it more maintainable
@@ -667,7 +667,7 @@ bool HWConformity::reduceExecSize( INST_LIST_ITER iter, G4_BB* bb )
667667
// You will need to do this ONLY when destination spans 2 registers, src1 is a word or byte and you expect channels to be turned off !!
668668
// currrently for instruction with pred or emask on pre-BDW
669669
bool specialCondForShootDown = ( dst && goodTwoGRFDst &&
670-
( inst->getPredicate() || ( bb->isInSimdFlow() && !inst->isWriteEnableInst() ) ) &&
670+
( inst->getPredicate() || ( !bb->isAllLaneActive() && !inst->isWriteEnableInst() ) ) &&
671671
oneGRFSrc[1] && ( IS_BTYPE( srcs[1]->getType() ) || IS_WTYPE( srcs[1]->getType() ) ) );
672672
if( specialCondForShootDown )
673673
{
@@ -764,7 +764,7 @@ bool HWConformity::reduceExecSize( INST_LIST_ITER iter, G4_BB* bb )
764764

765765
// can't split if inst is in SIMD flow and is not NoMask, or the inst has predicate
766766
// Have to introduce a temp that supports splitting instead
767-
if ((bb->isInSimdFlow() && !inst->isWriteEnableInst()) || inst->getPredicate())
767+
if ((!bb->isAllLaneActive() && !inst->isWriteEnableInst()) || inst->getPredicate())
768768
{
769769
saveDst( iter, scale, bb );
770770
INST_LIST_ITER tmpIter = iter;
@@ -993,7 +993,7 @@ void HWConformity::splitInstruction(INST_LIST_ITER iter, G4_BB* bb, bool compOpt
993993
// mov (16) r2.0<1>:uw 0:uw {Align1, NoMask} // 0:uw
994994
// mov (16) r2.0<1>:uw 0x1:uw {Align1} // 1:uw
995995
// this part is currently not used since we do not split inst with predicate or emask
996-
bool isSIMDCFInst = bb->isInSimdFlow() && !inst->isWriteEnableInst();
996+
bool isSIMDCFInst = !bb->isAllLaneActive() && !inst->isWriteEnableInst();
997997
G4_Declare *maskDcl = NULL;
998998
if (instPred || isSIMDCFInst)
999999
{
@@ -1388,7 +1388,7 @@ bool HWConformity::evenlySplitInst( INST_LIST_ITER iter, G4_BB* bb, bool checkOv
13881388
}
13891389

13901390
// set mask
1391-
bool needsMaskOffset = useARF || (bb->isInSimdFlow() && !inst->isWriteEnableInst());
1391+
bool needsMaskOffset = useARF || (!bb->isAllLaneActive() && !inst->isWriteEnableInst());
13921392
if (needsMaskOffset)
13931393
{
13941394
int newMaskOffset = origMaskOffset + (i == 0 ? 0 : currExSize);
@@ -1398,7 +1398,7 @@ bool HWConformity::evenlySplitInst( INST_LIST_ITER iter, G4_BB* bb, bool checkOv
13981398
if (newMask == InstOpt_NoOpt)
13991399
{
14001400
bool useMask = inst->getPredicate() || inst->getCondModBase() ||
1401-
(bb->isInSimdFlow() && !inst->isWriteEnableInst());
1401+
(!bb->isAllLaneActive() && !inst->isWriteEnableInst());
14021402
MUST_BE_TRUE(!useMask, "no legal emask found for the split instruction");
14031403
}
14041404
else
@@ -1517,7 +1517,7 @@ void HWConformity::moveSrcToGRF( INST_LIST_ITER it, uint32_t srcNum, uint16_t nu
15171517
( def_inst->getExecSize() == execSize ) &&
15181518
def_inst->getDst()->coverGRF( numGRF, execSize ) &&
15191519
def_inst->getDst()->checkGRFAlign() &&
1520-
( !bb->isInSimdFlow() || def_inst->isWriteEnableInst() ) )
1520+
( bb->isAllLaneActive() || def_inst->isWriteEnableInst() ) )
15211521
{
15221522

15231523
//inst->removeDefUse( Gen4_Operand_Number(srcNum + 1) );
@@ -1544,7 +1544,7 @@ void HWConformity::moveSrcToGRF( INST_LIST_ITER it, uint32_t srcNum, uint16_t nu
15441544
hs,
15451545
dcl->getElemType());
15461546
G4_INST* newInst = builder.createMov(
1547-
execSize, dstRegion, src, (bb->isInSimdFlow() ? InstOpt_WriteEnable : InstOpt_NoOpt), false);
1547+
execSize, dstRegion, src, (!bb->isAllLaneActive() ? InstOpt_WriteEnable : InstOpt_NoOpt), false);
15481548

15491549
// insert instruction and maintain def-use chain
15501550
bb->insert( it, newInst );

‎visa/RegAlloc.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1828,7 +1828,7 @@ bool LivenessAnalysis::writeWholeRegion(G4_BB* bb,
18281828
unsigned execSize = inst->getExecSize();
18291829
MUST_BE_TRUE(dst->getBase()->isRegVar(), ERROR_REGALLOC);
18301830

1831-
if( bb->isInSimdFlow() && !inst->isWriteEnableInst() && opt->getTarget() != VISA_3D )
1831+
if( !bb->isAllLaneActive() && !inst->isWriteEnableInst() && opt->getTarget() != VISA_3D )
18321832
{
18331833
// conservatively assume non-nomask instructions in simd control flow
18341834
// may not write the whole region
@@ -1911,7 +1911,7 @@ bool LivenessAnalysis::writeWholeRegion(G4_BB* bb,
19111911
G4_VarBase* flagReg,
19121912
const Options *opt)
19131913
{
1914-
if( bb->isInSimdFlow() && !inst->isWriteEnableInst() && opt->getTarget() != VISA_3D )
1914+
if( !bb->isAllLaneActive() && !inst->isWriteEnableInst() && opt->getTarget() != VISA_3D )
19151915
{
19161916
// conservatively assume non-nomask instructions in simd control flow
19171917
// may not write the whole region
@@ -1937,7 +1937,7 @@ void LivenessAnalysis::footprintDst(G4_BB* bb,
19371937
if (dstfootprint &&
19381938
!(i->isPartialWrite()) &&
19391939
((isLocal ||
1940-
bb->isInSimdFlow() == false ||
1940+
bb->isAllLaneActive() ||
19411941
i->isWriteEnableInst() == true) ||
19421942
gra.kernel.getOptions()->getTarget() == VISA_3D))
19431943
{

‎visa/Rematerialization.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -502,8 +502,8 @@ namespace vISA
502502

503503
// If uniqueDefBB is not under SIMD CF, current BB is under SIMD CF
504504
// then we can remat only if def has NoMask option set.
505-
if (!uniqueDefBB->isInSimdFlow() &&
506-
bb->isInSimdFlow() &&
505+
if (uniqueDefBB->isAllLaneActive() &&
506+
!bb->isAllLaneActive() &&
507507
!uniqueDefInst->isWriteEnableInst())
508508
{
509509
return false;

‎visa/SpillCode.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -500,7 +500,7 @@ void SpillManager::replaceSpilledFlagDst(G4_BB* bb,
500500
// Need to pre-load the spill GRF if the inst isn't going to write the full
501501
// spilled GRF variable.
502502
if (flagDcl->getNumberFlagElements() > inst->getExecSize() ||
503-
(bb->isInSimdFlow() && !inst->isWriteEnableInst()))
503+
(!bb->isAllLaneActive() && !inst->isWriteEnableInst()))
504504
{
505505
genRegMov(bb, it,
506506
spDcl->getRegVar(), 0,

‎visa/SpillManagerGMRF.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3893,7 +3893,7 @@ SpillManagerGRF::insertSpillFillCode (
38933893

38943894
for (BB_LIST_ITER it = fg.begin(); it != fg.end(); it++)
38953895
{
3896-
inSIMDCFContext_ = (*it)->isInSimdFlow();
3896+
inSIMDCFContext_ = !((*it)->isAllLaneActive());
38973897
bbId_ = (*it)->getId();
38983898
INST_LIST::iterator jt = (*it)->begin();
38993899

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