acc substitution update

acc substitution update

Author: bcheng0127

visa/BuildIR.h

@@ -604,6 +604,8 @@ class IR_Builder {
     return kernel.getBoolKernelAttr(Attributes::ATTR_LTOInvokeOptTarget);
   }
 
+  bool isGRFDstAligned(G4_Operand *dst, int alignByte) const;
+
   //
   // Check if opnd is or can be made "alignByte"-byte aligned.
   // These functions will change the underlying variable's alignment

visa/BuildIRImpl.cpp

@@ -165,6 +165,63 @@ void IR_Builder::bindInputDecl(
   }
 }
 
+bool IR_Builder::isGRFDstAligned(G4_Operand* opnd, int alignByte) const
+{
+  bool isAligned = true;
+  unsigned short offset = 0;
+  int type_size = opnd->getTypeSize();
+  G4_Declare *dcl = NULL;
+
+  dcl = opnd->getBase()->asRegVar()->getDeclare();
+  while (dcl && dcl->getAliasDeclare()) {
+    if (dcl->getSubRegAlign() != Any &&
+        (((dcl->getSubRegAlign() * 2) >= alignByte &&
+          (dcl->getSubRegAlign() * 2) % alignByte != 0) ||
+         ((dcl->getSubRegAlign() * 2) < alignByte &&
+          alignByte % (dcl->getSubRegAlign() * 2) != 0))) {
+      isAligned = false;
+      break;
+    }
+    offset += (unsigned short)dcl->getAliasOffset();
+    dcl = dcl->getAliasDeclare();
+  }
+
+  if (dcl && dcl->getRegVar() && dcl->getRegVar()->isPhyRegAssigned()) {
+    offset += static_cast<unsigned short>(dcl->getRegVar()->getByteAddr(*this));
+  }
+
+  if (!isAligned) {
+    return false;
+  }
+
+  if (opnd->isDstRegRegion()) {
+    if (opnd->asDstRegRegion()->getRegAccess() != Direct) {
+      isAligned = false;
+    }
+    offset += opnd->asDstRegRegion()->getRegOff() * numEltPerGRF<Type_UB>() +
+              opnd->asDstRegRegion()->getSubRegOff() * type_size;
+  }
+
+  if (offset % alignByte != 0) {
+    return false;
+  }
+
+  if (dcl && dcl->getRegFile() == G4_GRF) {
+    if (dcl->getSubRegAlign() == Any ||
+        ((dcl->getSubRegAlign() * 2) < alignByte &&
+         alignByte % (dcl->getSubRegAlign() * 2) == 0)) {
+      isAligned = false;
+    } else if ((dcl->getSubRegAlign() * 2) < alignByte ||
+               (dcl->getSubRegAlign() * 2) % alignByte != 0) {
+      isAligned = false;
+    }
+  } else {
+    isAligned = false;
+  }
+
+  return isAligned;
+}
+
 // check if an operand is aligned to <alignByte>
 bool IR_Builder::tryToAlignOperand(G4_Operand *opnd, unsigned short &offset,
                                    int alignByte) const {

visa/G4_IR.cpp

@@ -7564,7 +7564,15 @@ bool G4_INST::canSrcBeAccAfterHWConform(Gen4_Operand_Number opndNum) const {
       } else {
         // If the destination offset is not GRF aligned, such as has sub
         // register offset, the src cannot be replaced with ACC
-        if (!builder.tryToAlignOperand(dst,
+        if (builder.enableACCBeforRA() &&
+            !builder.enablePreSchedACC() && builder.supports4GRFAlign()) {
+          // Before RA, align may affect the RA result, so don't do
+          // alignment, just check if it's aligned
+          if (!builder.isGRFDstAligned(dst,
+                                    getBuilder().numEltPerGRF<Type_UB>())) {
+            return false;
+          }
+        } else if (!builder.tryToAlignOperand(dst,
                                        getBuilder().numEltPerGRF<Type_UB>())) {
           return false;
         }