[Autobackout][FunctionalRegression]Revert of change: 83f5c59: Change default float controls

Switch default denormals handling from flush-to-zero into retain

Author: sys-igc

IGC/VectorCompiler/lib/GenXCodeGen/GenXFloatControl.cpp

@@ -66,10 +66,8 @@ bool GenXFloatControl::runOnFunction(Function &F) {
          CRBits::SinglePrecisionDenorm | CRBits::HalfPrecisionDenorm;
   // Default float control:
   //   rounding mode = nearest even
-  //   denormals = retain
-  uint32_t FloatControl = CRBits::RTNE | CRBits::DoublePrecisionDenorm |
-                          CRBits::SinglePrecisionDenorm |
-                          CRBits::HalfPrecisionDenorm;
+  //   denormals = flush
+  uint32_t FloatControl = CRBits::RTNE;
   const auto *Subtarget = &getAnalysis<TargetPassConfig>()
                                .getTM<GenXTargetMachine>()
                                .getGenXSubtarget();

IGC/VectorCompiler/test/GenXFloatControl/float_control.ll

@@ -15,19 +15,10 @@
 ; RUN: FileCheck %s --check-prefix=CHECK-VISA
 
 ; CHECK-LABEL: define dllexport spir_kernel void @kernel
-; CHECK-NEXT: [[AND_READ_PREDEF:[^ ]+]] = call <4 x i32> @llvm.genx.read.predef.reg.v4i32.v4i32(i32 14, <4 x i32> undef)
-; CHECK-NEXT: [[AND_RDREGION:[^ ]+]] = call i32 @llvm.genx.rdregioni.i32.v4i32.i16(<4 x i32> [[AND_READ_PREDEF]], i32 0, i32 1, i32 1, i16 0, i32 undef)
-; CHECK-NEXT: [[AND:[^ ]+]] = and i32 [[AND_RDREGION]], -1265
-; CHECK-NEXT: [[AND_WRREGION:[^ ]+]] = call <4 x i32> @llvm.genx.wrregioni.v4i32.i32.i16.i1(<4 x i32> [[AND_READ_PREDEF]], i32 [[AND]], i32 0, i32 1, i32 1, i16 0, i32 undef, i1 true)
-; CHECK-NEXT: call <4 x i32> @llvm.genx.write.predef.reg.v4i32.v4i32(i32 14, <4 x i32> [[AND_WRREGION]])
-; CHECK-NEXT: [[OR_READ_PREDEF:[^ ]+]] = call <4 x i32> @llvm.genx.read.predef.reg.v4i32.v4i32(i32 14, <4 x i32> undef)
-; CHECK-NEXT: [[OR_RDREGION:[^ ]+]] = call i32 @llvm.genx.rdregioni.i32.v4i32.i16(<4 x i32> [[OR_READ_PREDEF]], i32 0, i32 1, i32 1, i16 0, i32 undef)
-; CHECK-NEXT: [[OR:[^ ]+]] = or i32 [[OR_RDREGION]], 1216
-; CHECK-NEXT: [[OR_WRREGION:[^ ]+]] = call <4 x i32> @llvm.genx.wrregioni.v4i32.i32.i16.i1(<4 x i32> [[OR_READ_PREDEF]], i32 [[OR]], i32 0, i32 1, i32 1, i16 0, i32 undef, i1 true)
+; CHECK-NOT: predef
 ; CHECK:     ret
 ; CHECK-VISA-LABEL: .function "kernel_BB_0"
-; CHECK-VISA:      and (M1, 1) %cr0(0,0)<1> %cr0(0,0)<0;1,0> 0xfffffb0f:d
-; CHECK-VISA-NEXT: or (M1, 1) %cr0(0,0)<1> %cr0(0,0)<0;1,0> 0x4c0:d
+; CHECK-VISA-NOT:  %cr0
 ; CHECK-VISA:      ret (M1, 1)
 define dllexport spir_kernel void @kernel(i32 %a, i64 %privBase) #0 {
   call spir_func i32 @stackcall(i32 %a) #1

IGC/VectorCompiler/test/VisaRegAlloc/no_coalescing.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2021-2024 Intel Corporation
+; Copyright (C) 2021 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -13,15 +13,17 @@
 ; RUN: -vc-fg-dump-prefix=%basename_t_ \
 ; RUN: -finalizer-opts='-generateDebugInfo' -o /dev/null
 
+; COM: These checks are brittle and differ between LLVM versions.
+; COM: Currently accounted for with {{(<pre-llvm11-val>|<llvm11-val>)}} regexp syntax.
+; FIXME: Return unconditional checks once LLVM version is unified for IGC.
+
 ; RUN: FileCheck %s --input-file=%basename_t_M_.regalloc --check-prefix=CHECK_NOCOALESC
-; CHECK_NOCOALESC:      [t7] (4 bytes, length 33) arg1:[0,33)
-; CHECK_NOCOALESC-NEXT: [t6] (4 bytes, length 27) arg:[0,27)
-; CHECK_NOCOALESC-NEXT: [v34] (64 bytes, length 6) :[25,31)
-; CHECK_NOCOALESC-NEXT: [v32] (16 bytes, length 3) :[10,13)
-; CHECK_NOCOALESC-NEXT: [v33] (16 bytes, length 3) :[20,23)
-; CHECK_NOCOALESC-NEXT: [v35] (64 bytes, length 2) :[27,29)
-; CHECK_NOCOALESC-NEXT: [v36] (64 bytes, length 2) :[29,31)
-; CHECK_NOCOALESC-NEXT: [v37] (64 bytes, length 2) :[31,33)
+; CHECK_NOCOALESC: [t7] (4 bytes, length 13) arg1:[0,13)
+; CHECK_NOCOALESC-NEXT: [t6] (4 bytes, length 7) arg:[0,7)
+; CHECK_NOCOALESC-NEXT: [v32] (64 bytes, length {{(4|6)}}) :[5,{{(9|11)}})
+; CHECK_NOCOALESC-NEXT: [v33] (64 bytes, length {{(4|2)}}) :[7,{{(11|9)}})
+; CHECK_NOCOALESC-NEXT: [v34] (64 bytes, length 2) :[9,11)
+; CHECK_NOCOALESC-NEXt: [v35] (64 bytes, length 2) :[11,13)
 ; CHECK_NOCOALESC: Register pressure (bytes):
 ; CHECK_NOCOALESC: Flag pressure (bytes):
 
@@ -32,13 +34,11 @@
 ; RUN: -finalizer-opts='-generateDebugInfo' -o /dev/null
 
 ; RUN: FileCheck %s --input-file=%basename_t_M_.regalloc --check-prefix=CHECK_COALESC
-; CHECK_COALESC:      [t7] (4 bytes, length 33) arg1:[0,33)
-; CHECK_COALESC-NEXT: [t6] (4 bytes, length 27) arg:[0,27)
-; CHECK_COALESC-NEXT: [v34] (64 bytes, length 6) :[25,31)
-; CHECK_COALESC-NEXT: [v35] (64 bytes, length 4) :[27,31)
-; CHECK_COALESC-NEXT: [v32] (16 bytes, length 3) :[10,13)
-; CHECK_COALESC-NEXT: [v33] (16 bytes, length 3) :[20,23)
-; CHECK_COALESC-NEXT: [v36] (64 bytes, length 2) :[31,33)
+; CHECK_COALESC: [t7] (4 bytes, length 13) arg1:[0,13)
+; CHECK_COALESC-NEXT: [t6] (4 bytes, length 7) arg:[0,7)
+; CHECK_COALESC-NEXT: [v{{(33|32)}}] (64 bytes, length 6) :[5,11)
+; CHECK_COALESC-NEXT: [v{{(32|33)}}] (64 bytes, length 4) :[7,11)
+; CHECK_COALESC-NEXt: [v34] (64 bytes, length 2) :[11,13)
 ; CHECK_COALESC: Register pressure (bytes):
 ; CHECK_COALESC: Flag pressure (bytes):
 

IGC/VectorCompiler/test/VisaRegAlloc/reg_alloc_dump_basic.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2021-2024 Intel Corporation
+; Copyright (C) 2021 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -15,13 +15,11 @@
 ; COM: these checks are potentially brittle. Though, the size of the test is
 ; COM: small and it should be easy to modify if problem arise
 ; RUN: FileCheck %s --input-file=%basename_t_M_.regalloc
-; CHECK:      [t7] (4 bytes, length 31) arg1:[0,31)
-; CHECK-NEXT: [t6] (4 bytes, length 27) arg:[0,27)
-; CHECK-NEXT: [v34] (64 bytes, length 4) :[25,29)
-; CHECK-NEXT: [v32] (16 bytes, length 3) :[10,13)
-; CHECK-NEXT: [v33] (16 bytes, length 3) :[20,23)
-; CHECK-NEXT: [v35] (64 bytes, length 2) :[27,29)
-; CHECK-NEXT: [v36] (64 bytes, length 2) :[29,31)
+; CHECK: [t7] (4 bytes, length 11) arg1:[0,11)
+; CHECK-NEXT: [t6] (4 bytes, length 7) arg:[0,7)
+; CHECK-NEXT: [v32] (64 bytes, length 4) :[5,9)
+; CHECK-NEXT: [v33] (64 bytes, length 2) :[7,9)
+; CHECK-NEXT: [v34] (64 bytes, length 2) :[9,11)
 ; CHECK: Register pressure (bytes):
 ; CHECK: Flag pressure (bytes):