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igorban-inteligcbot
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Lower Bfloat ceil/floor intrinsics
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+54
-2
lines changed

2 files changed

+54
-2
lines changed

IGC/VectorCompiler/lib/GenXCodeGen/GenXBFloatLowering.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
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/*========================== begin_copyright_notice ============================
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3-
Copyright (C) 2023-2024 Intel Corporation
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Copyright (C) 2023-2025 Intel Corporation
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SPDX-License-Identifier: MIT
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@@ -239,6 +239,10 @@ void GenXBFloatLowering::visitCallInst(CallInst &Inst) {
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switch (IID) {
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default:
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return;
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case Intrinsic::ceil:
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case Intrinsic::floor:
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case Intrinsic::round:
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case Intrinsic::trunc:
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case GenXIntrinsic::genx_sat:
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break;
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case Intrinsic::cos:

IGC/VectorCompiler/test/GenXBFloatLowering/intrinsics.ll

Lines changed: 49 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
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;
3-
; Copyright (C) 2023 Intel Corporation
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; Copyright (C) 2023-2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
@@ -30,6 +30,12 @@ declare <8 x bfloat> @llvm.fmuladd.v8bf16(<8 x bfloat>, <8 x bfloat>, <8 x bfloa
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declare <8 x i32> @llvm.fptosi.sat.v8i32.v8bf16(<8 x bfloat>)
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declare <8 x i32> @llvm.fptoui.sat.v8i32.v8bf16(<8 x bfloat>)
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declare <8 x bfloat> @llvm.ceil.v8bf16(<8 x bfloat>)
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declare <8 x bfloat> @llvm.floor.v8bf16(<8 x bfloat>)
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declare <8 x bfloat> @llvm.round.v8bf16(<8 x bfloat>)
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declare <8 x bfloat> @llvm.trunc.v8bf16(<8 x bfloat>)
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; CHECK-LABEL: test_sat
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define <8 x bfloat> @test_sat(<8 x bfloat> %src) {
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; CHECK: [[EXT:%[^ ]+]] = fpext <8 x bfloat> %src to <8 x float>
@@ -196,3 +202,45 @@ define <8 x i32> @test_fptoui_sat(<8 x bfloat> %src) {
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%res = call <8 x i32> @llvm.fptoui.sat.v8i32.v8bf16(<8 x bfloat> %src)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test_ceil
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define <8 x bfloat> @test_ceil(<8 x bfloat> %src) {
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; CHECK: [[EXT:%[^ ]+]] = fpext <8 x bfloat> %src to <8 x float>
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; CHECK: [[RES:%[^ ]+]] = call fast <8 x float> @llvm.ceil.v8f32(<8 x float> [[EXT]])
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; CHECK: [[TRUNC:%[^ ]+]] = fptrunc <8 x float> [[RES]] to <8 x bfloat>
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; CHECK: ret <8 x bfloat> [[TRUNC]]
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%res = call fast <8 x bfloat> @llvm.ceil.v8bf16(<8 x bfloat> %src)
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ret <8 x bfloat> %res
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}
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; CHECK-LABEL: test_floor
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define <8 x bfloat> @test_floor(<8 x bfloat> %src) {
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; CHECK: [[EXT:%[^ ]+]] = fpext <8 x bfloat> %src to <8 x float>
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; CHECK: [[RES:%[^ ]+]] = call fast <8 x float> @llvm.floor.v8f32(<8 x float> [[EXT]])
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; CHECK: [[TRUNC:%[^ ]+]] = fptrunc <8 x float> [[RES]] to <8 x bfloat>
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; CHECK: ret <8 x bfloat> [[TRUNC]]
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%res = call fast <8 x bfloat> @llvm.floor.v8bf16(<8 x bfloat> %src)
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ret <8 x bfloat> %res
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}
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; CHECK-LABEL: test_round
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define <8 x bfloat> @test_round(<8 x bfloat> %src) {
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; CHECK: [[EXT:%[^ ]+]] = fpext <8 x bfloat> %src to <8 x float>
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; CHECK: [[RES:%[^ ]+]] = call fast <8 x float> @llvm.round.v8f32(<8 x float> [[EXT]])
230+
; CHECK: [[TRUNC:%[^ ]+]] = fptrunc <8 x float> [[RES]] to <8 x bfloat>
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; CHECK: ret <8 x bfloat> [[TRUNC]]
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%res = call fast <8 x bfloat> @llvm.round.v8bf16(<8 x bfloat> %src)
233+
ret <8 x bfloat> %res
234+
}
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; CHECK-LABEL: test_trunc
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define <8 x bfloat> @test_trunc(<8 x bfloat> %src) {
238+
; CHECK: [[EXT:%[^ ]+]] = fpext <8 x bfloat> %src to <8 x float>
239+
; CHECK: [[RES:%[^ ]+]] = call fast <8 x float> @llvm.trunc.v8f32(<8 x float> [[EXT]])
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; CHECK: [[TRUNC:%[^ ]+]] = fptrunc <8 x float> [[RES]] to <8 x bfloat>
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; CHECK: ret <8 x bfloat> [[TRUNC]]
242+
%res = call fast <8 x bfloat> @llvm.trunc.v8bf16(<8 x bfloat> %src)
243+
ret <8 x bfloat> %res
244+
}
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