Add new Relocation Type R_PER_THREAD_PAYLOAD_OFFSET_32

Also refactor vISA::RelocationEntry create API

Change-Id: Ic6dcd8971396651d8f1e54e7606d6c33c3588f04

Author: DianaChen

visa/BuildIR.h

@@ -1625,6 +1625,18 @@ class IR_Builder {
         return newImm;
     }
 
+    //
+    // Create immediate operand without looking up hash table. This operand
+    // is a relocatable immediate type. Specify the value of this imm field,
+    // which will present in the output instruction's imm value.
+    //
+    G4_Reloc_Imm* createRelocImm(int64_t immval, G4_Type ty)
+    {
+        G4_Reloc_Imm* newImm;
+        newImm = new (mem)G4_Reloc_Imm(immval, ty);
+        return newImm;
+    }
+
     //
     // return the label operand; create one if not found
     //

visa/FlowGraph.cpp

@@ -7036,6 +7036,13 @@ FlowGraph::~FlowGraph()
     }
 }
 
+RelocationEntry& RelocationEntry::createRelocation(G4_Kernel& kernel, G4_INST& inst,
+    int opndPos, const std::string& symbolName, RelocationType type)
+{
+    kernel.getRelocationTable().emplace_back(RelocationEntry(&inst, opndPos, type, symbolName));
+    return kernel.getRelocationTable().back();
+}
+
 KernelDebugInfo* G4_Kernel::getKernelDebugInfo()
 {
     if (kernelDbgInfo == nullptr)
@@ -7399,24 +7406,42 @@ void RelocationEntry::doRelocation(const G4_Kernel& kernel, void* binary, uint32
 
 uint32_t RelocationEntry::getTargetOffset(const IR_Builder& builder) const
 {
-    // currently we only support relocation on mov instruction
-    assert(inst->isMov());
+    // instruction being relocated must not be compacted, or the offset need to be re-adjusted
+    // FIXME: This only check if vISA force to compact the instruction, it cannot make sure
+    // the Binary encoder won't compact it
     assert(inst->isCompactedInst() == false);
-    auto src0 = inst->getSrc(0);
-    assert(src0->isRelocImm() && ((src0->getType() == Type_UD) || (src0->getType() == Type_UQ)));
 
-    // When src0 type is 64 bits:
-    //  On PreGen12:
-    //   Src0.imm[31:0] mapped to Instruction [95:64]
-    //   Src0.imm[63:32] mapped to Instruction [127:96]
-    //  On Gen12+:
-    //   Src0.imm[31:0] mapped to Instruction [127:96]
-    //   Src0.imm[63:32] mapped to Instruction [95:64]
-
-    // When src0 type is 32 bits:
-    //   Src0.imm[31:0] mapped to instruction [127:96]
+    G4_Operand* target_operand = inst->getSrc(opndPos);
+    assert(target_operand->isRelocImm());
+
+    switch (inst->opcode()) {
+    case G4_mov:
+        // When src0 type is 64 bits:
+        //  On PreGen12:
+        //   Src0.imm[31:0] mapped to Instruction [95:64]
+        //   Src0.imm[63:32] mapped to Instruction [127:96]
+        //  On Gen12+:
+        //   Src0.imm[31:0] mapped to Instruction [127:96]
+        //   Src0.imm[63:32] mapped to Instruction [95:64]
+        // When src0 type is 32 bits:
+        //   Src0.imm[31:0] mapped to instruction [127:96]
+        assert((target_operand->getType() == Type_UD) || (target_operand->getType() == Type_UQ));
+        assert(opndPos == 0);
+        return (target_operand->getType() == Type_UD) ? 12 : 8;
+
+    case G4_add:
+        // add instruction cannot have 64-bit imm
+        assert(relocType != R_SYM_ADDR && relocType != R_SYM_ADDR_32_HI);
+        assert(opndPos == 1);
+        // Src1.imm[31:0] mapped to Instruction [127:96]
+        return 12;
+    default:
+        break;
+    }
 
-    return (src0->getType() == Type_UD) ? 12 : 8;
+    // currently we only support relocation on mov or add instruction
+    assert(false && "Unreachable");
+    return 0;
 }
 
 void RelocationEntry::dump() const
@@ -7438,6 +7463,9 @@ void RelocationEntry::dump() const
         case RelocationType::R_SYM_ADDR_32_HI:
             std::cerr << "R_SYM_ADDR_32_HI: symbol name = " << symName;
             break;
+        case RelocationType::R_PER_THREAD_PAYLOAD_OFFSET_32:
+            std::cerr << "R_PER_THREAD_PAYLOAD_OFFSET_32: symbol name = " << symName;
+            break;
     }
     std::cerr << "\n";
 }

visa/FlowGraph.h

@@ -53,6 +53,7 @@ class PhyRegSummary;
 //
 
 class G4_BB;
+class G4_Kernel;
 class FlowGraph;
 class KernelDebugInfo;
 class VarSplitPass;
@@ -672,7 +673,6 @@ typedef std::pair<BB_LIST_ITER, BB_LIST_ITER> GRAPH_CUT_BOUNDS;
 namespace vISA
 {
 
-class G4_Kernel; // forward declaration
 class FlowGraph
 {
     // Data
@@ -1363,11 +1363,8 @@ class RelocationEntry
         inst(i), opndPos(pos), relocType(type), symName(symbolName){}
 
 public:
-    static RelocationEntry createSymbolAddrReloc(G4_INST* inst, int opndPos, const std::string& symbolName, RelocationType type)
-    {
-        RelocationEntry entry(inst, opndPos, type, symbolName);
-        return entry;
-    }
+    static RelocationEntry& createRelocation(G4_Kernel& kernel, G4_INST& inst,
+        int opndPos, const std::string& symbolName, RelocationType type);
 
     G4_INST* getInst() const
     {
@@ -1389,6 +1386,8 @@ class RelocationEntry
                 return "R_SYM_ADDR_32";
             case RelocationType::R_SYM_ADDR_32_HI:
                 return "R_SYM_ADDR_32_HI";
+            case RelocationType::R_PER_THREAD_PAYLOAD_OFFSET_32:
+                return "R_PER_THREAD_PAYLOAD_OFFSET_32";
             default:
                 assert(false && "unhandled relocation type");
                 return "";
@@ -1402,12 +1401,6 @@ class RelocationEntry
 
     const std::string& getSymbolName() const
     {
-        bool isValidRelocType =
-            relocType == RelocationType::R_SYM_ADDR ||
-            relocType == RelocationType::R_SYM_ADDR_32 ||
-            relocType == RelocationType::R_SYM_ADDR_32_HI;
-
-        assert(isValidRelocType && "invalid relocation type");
         return symName;
     }
 
@@ -1627,11 +1620,6 @@ class G4_Kernel
         m_hasIndirectCall = true;
     }
 
-    void addRelocation(RelocationEntry& entry)
-    {
-        relocationTable.push_back(entry);
-    }
-
     RelocationTableTy& getRelocationTable()
     {
         return relocationTable;

visa/Gen4_IR.hpp

@@ -2720,9 +2720,15 @@ class G4_Reloc_Imm : public G4_Imm
     void *operator new(size_t sz, Mem_Manager& m){ return m.alloc(sz); }
     bool isRelocImm() const override { return true; }
 
+    // G4_Reloc_Imm is the relocation target field. If the value is not given,
+    // a magic number 0x6e10ca2e will present in final output
     G4_Reloc_Imm(G4_Type ty) : G4_Imm((int64_t)0x6e10ca2e, ty)
     {
     }
+
+    G4_Reloc_Imm(int64_t val, G4_Type ty) : G4_Imm(val, ty)
+    {
+    }
 };
 
 //

visa/TranslationInterface.cpp

@@ -2424,8 +2424,7 @@ int IR_Builder::translateVISACFSymbolInst(const std::string& symbolName, G4_DstR
         auto* privateMemPatch = createRelocImm(Type_UD);
         dst->setType(Type_UD);
         G4_INST* mov = createMov(1, dst, privateMemPatch, InstOpt_WriteEnable, true);
-        RelocationEntry relocEntry = RelocationEntry::createSymbolAddrReloc(mov, 0, symbolName, GenRelocType::R_SYM_ADDR_32);
-        kernel.addRelocation(relocEntry);
+        RelocationEntry::createRelocation(kernel, *mov, 0, symbolName, GenRelocType::R_SYM_ADDR_32);
     }
     else if (noInt64() || needSwap64ImmLoHi())
     {
@@ -2440,11 +2439,8 @@ int IR_Builder::translateVISACFSymbolInst(const std::string& symbolName, G4_DstR
         auto dstHi = createDst(dst->getBase(), dst->getRegOff(), dst->getSubRegOff() * 2 + 1, 1, Type_UD);
         G4_INST* movHi = createMov(1, dstHi, funcAddrHigh, InstOpt_WriteEnable, true);
 
-        RelocationEntry relocEntryLo = RelocationEntry::createSymbolAddrReloc(movLo, 0, symbolName, GenRelocType::R_SYM_ADDR_32);
-        kernel.addRelocation(relocEntryLo);
-
-        RelocationEntry relocEntryHi = RelocationEntry::createSymbolAddrReloc(movHi, 0, symbolName, GenRelocType::R_SYM_ADDR_32_HI);
-        kernel.addRelocation(relocEntryHi);
+        RelocationEntry::createRelocation(kernel, *movLo, 0, symbolName, GenRelocType::R_SYM_ADDR_32);
+        RelocationEntry::createRelocation(kernel, *movHi, 0, symbolName, GenRelocType::R_SYM_ADDR_32_HI);
 
     }
     else
@@ -2453,8 +2449,7 @@ int IR_Builder::translateVISACFSymbolInst(const std::string& symbolName, G4_DstR
         auto funcAddr = createRelocImm(Type_UQ);
         auto movInst = createMov(1, dst, funcAddr, InstOpt_WriteEnable, true);
 
-        RelocationEntry relocEntry = RelocationEntry::createSymbolAddrReloc(movInst, 0, symbolName, GenRelocType::R_SYM_ADDR);
-        kernel.addRelocation(relocEntry);
+        RelocationEntry::createRelocation(kernel, *movInst, 0, symbolName, GenRelocType::R_SYM_ADDR);
     }
 
 #if defined(MEASURE_COMPILATION_TIME) && defined(TIME_IR_CONSTRUCTION)

visa/VISAKernelImpl.cpp

@@ -8065,6 +8065,8 @@ int VISAKernelImpl::GetGenRelocEntryBuffer(void *&buffer, unsigned int &byteSize
         assert((buffer_p->r_offset > inst->getGenOffset()) && (buffer_p->r_offset < inst->getGenOffset() + BYTES_PER_INST));
 
         assert(reloc.getSymbolName().size() <= MAX_SYMBOL_NAME_LENGTH);
+        // clean the buffer first
+        memset(buffer_p->r_symbol, '0', MAX_SYMBOL_NAME_LENGTH);
         strcpy_s(buffer_p->r_symbol, MAX_SYMBOL_NAME_LENGTH, reloc.getSymbolName().c_str());
         ++buffer_p;
     }

visa/include/RelocationInfo.h

@@ -61,9 +61,10 @@ typedef struct {
 /// GenRelocType - Specify the relocation's type
 enum GenRelocType {
     R_NONE = 0,
-    R_SYM_ADDR = 1,      //64-bit type address
-    R_SYM_ADDR_32 = 2,   //lower 32-bit of 64-bit address.
-    R_SYM_ADDR_32_HI = 3 //higher 32bits of 64-bit address
+    R_SYM_ADDR                     = 1, // 64-bit type address
+    R_SYM_ADDR_32                  = 2, // 32-bit address or lower 32-bit of a 64-bit address.
+    R_SYM_ADDR_32_HI               = 3, // higher 32bits of 64-bit address
+    R_PER_THREAD_PAYLOAD_OFFSET_32 = 4  // 32-bit field of payload offset of per-thread data
 };
 
 /// GenRelocEntry - An relocation table entry