Refactor vISA instruction option setter functions.

weiyu-chen · sys_zuul · commit 354256e38029 · 2020-02-05T18:22:32.000-08:00
Change-Id: I81bde0776f6af561c9a60cb85524aed9725ae2a2
diff --git a/visa/BinaryEncodingIGA.cpp b/visa/BinaryEncodingIGA.cpp
@@ -658,8 +658,9 @@ void BinaryEncodingIGA::DoAll()
                         nullptr, G4_nop, nullptr, false, 1, nullptr, nullptr, nullptr, InstOpt_NoCompact));
         }
         // set all instruction to be NoCompact
-        for (auto inst : *first_bb) {
-            inst->setOptions(inst->getOption() | InstOpt_NoCompact);
+        for (auto inst : *first_bb)
+        {
+            inst->setOptionOn(InstOpt_NoCompact);
         }
     }
 
diff --git a/visa/Gen4_IR.cpp b/visa/Gen4_IR.cpp
@@ -1118,7 +1118,13 @@ uint16_t G4_INST::getMaskOffset() const
 {
     unsigned maskOption = (this->getOption() & InstOpt_QuarterMasks);
 
-    switch(maskOption)
+    if (!builder.hasNibCtrl())
+    {
+        assert(maskOption != InstOpt_M4 && maskOption != InstOpt_M12 && maskOption != InstOpt_M20 &&
+            maskOption != InstOpt_M28 && "nibCtrl is not supported on this platform");
+    }
+
+    switch (maskOption)
     {
     case InstOpt_NoOpt:
         return 0;
@@ -1139,7 +1145,7 @@ uint16_t G4_INST::getMaskOffset() const
     case InstOpt_M28:
         return 28;
     default:
-        MUST_BE_TRUE( 0, "Incorrect instruction execution mask" );
+        MUST_BE_TRUE(0, "Incorrect instruction execution mask");
         return 0;
     }
 }
diff --git a/visa/Gen4_IR.hpp b/visa/Gen4_IR.hpp
@@ -848,46 +848,35 @@ class G4_INST
 
     void computeARFRightBound();
 
+    static bool isMaskOption(G4_InstOption opt)
+    {
+        return (opt & InstOpt_QuarterMasks) != 0;
+    }
+
     void setOptions(unsigned int o)
     {
         unsigned int oldMaskOffset = getMaskOffset();
         option = o;
         unsigned int newMaskOffset = getMaskOffset();
 
-        if( oldMaskOffset != newMaskOffset )
+        if (oldMaskOffset != newMaskOffset)
         {
             // Change in mask offset requires change in
             // bounds for pred/cond mod/impl acc src/dst
             computeARFRightBound();
         }
     }
 
-    void setOptionOn(unsigned int o)
+    void setOptionOn(G4_InstOption o)
     {
-        unsigned int oldMaskOffset = getMaskOffset();
+        assert(!isMaskOption(o) && "use setMaskOption() to change emask instead");
         option |= o;
-        unsigned int newMaskOffset = getMaskOffset();
-
-        if( oldMaskOffset != newMaskOffset )
-        {
-            // Change in mask offset requires change in
-            // bounds for pred/cond mod/impl acc src/dst
-            computeARFRightBound();
-        }
     }
 
-    void setOptionOff(unsigned int o)
+    void setOptionOff(G4_InstOption o)
     {
-        unsigned int oldMaskOffset = getMaskOffset();
+        assert(!isMaskOption(o) && "use setMaskOption() to change emask instead");
         option &= (~o);
-        unsigned int newMaskOffset = getMaskOffset();
-
-        if( oldMaskOffset != newMaskOffset )
-        {
-            // Change in mask offset requires change in
-            // bounds for pred/cond mod/impl acc src/dst
-            computeARFRightBound();
-        }
     }
     unsigned int getOption() const {return option;}
     unsigned int getMaskOption() const {return option & InstOpt_Masks;}
@@ -899,6 +888,19 @@ class G4_INST
         setOptions((option & ~InstOpt_QuarterMasks) | opt);
     }
 
+    void setNoMask(bool clearEMask)
+    {
+        if (clearEMask)
+        {
+            // Clear the M0/M4/M8 emask as well
+            setOptions((getOption() & ~InstOpt_Masks) | InstOpt_WriteEnable);
+        }
+        else
+        {
+            setOptionOn(InstOpt_WriteEnable);
+        }
+    }
+
     bool is1QInst() const { return execSize == 8 && getMaskOffset() == 0; }
     bool isWriteEnableInst() const { return (option & InstOpt_WriteEnable) ? true : false; }
     bool isYieldInst() const { return (option & InstOpt_Switch) ? true : false; }
diff --git a/visa/HWConformity.cpp b/visa/HWConformity.cpp
@@ -207,10 +207,10 @@ G4_DstRegRegion* HWConformity::insertMovAfter( INST_LIST_ITER& it, G4_DstRegRegi
         inst->setSaturate(false);
     }
 
-    inst->setExecSize( newExecSize );
+    inst->setExecSize(newExecSize);
     if (newExecSize == 1)
     {
-        inst->setOptions((inst->getOption() & ~InstOpt_Masks ) | InstOpt_WriteEnable);
+        inst->setNoMask(true);
     }
 
     return builder.Create_Dst_Opnd_From_Dcl( dcl, scale);
@@ -945,7 +945,7 @@ bool HWConformity::fixLine(INST_LIST_ITER it, G4_BB *bb)
             G4_INST* newInst = builder.createMov(mov_size, new_dst_opnd, src0, InstOpt_NoOpt, false);
             if (bb->isInSimdFlow())
             {
-                newInst->setOptions((newInst->getOption() & ~InstOpt_Masks) | InstOpt_WriteEnable);
+                newInst->setNoMask(true);
             }
             bb->insert(it, newInst);
             inst->setSrc(new_src0_opnd, 0);
@@ -2322,7 +2322,7 @@ bool HWConformity::fixMULInst( INST_LIST_ITER &i, G4_BB *bb )
 
     if (bb->isInSimdFlow())
     {
-        inst->setOptions((inst->getOption() & ~InstOpt_Masks) | InstOpt_WriteEnable);
+        inst->setNoMask(true);
     }
 
     if (pred != NULL) {
@@ -2663,7 +2663,7 @@ void HWConformity::fixMULHInst( INST_LIST_ITER &i, G4_BB *bb )
 
     if (bb->isInSimdFlow())
     {
-        newMul->setOptions( ( inst_opt & ~InstOpt_Masks ) | InstOpt_WriteEnable );
+        newMul->setNoMask(true);
     }
     inst->setOpcode( G4_mach );
 
diff --git a/visa/Optimizer.cpp b/visa/Optimizer.cpp
@@ -6795,7 +6795,7 @@ bool Optimizer::foldPseudoAndOr(G4_BB* bb, INST_LIST_ITER& ii)
                     inst->isSplitSend() &&
                     !(inst->getSrc(1)->isNullReg()))
                 {
-                    inst->setOptions(inst->getOption() | InstOpt_NoPreempt);
+                    inst->setOptionOn(InstOpt_NoPreempt);
                 }
 
                 if (inst->isSend() && !inst->isNoPreemptInst() && builder.needsNoPreemptR2ForSend())
@@ -6806,7 +6806,7 @@ bool Optimizer::foldPseudoAndOr(G4_BB* bb, INST_LIST_ITER& ii)
                         unsigned LB = Src0->getLinearizedStart();
                         if (LB == 2 * GENX_GRF_REG_SIZ)
                         {
-                            inst->setOptions(inst->getOption() | InstOpt_NoPreempt);
+                            inst->setOptionOn(InstOpt_NoPreempt);
                         }
                     }
                 }
diff --git a/visa/ReduceExecSize.cpp b/visa/ReduceExecSize.cpp
@@ -1048,7 +1048,7 @@ void HWConformity::splitInstruction(INST_LIST_ITER iter, G4_BB* bb, bool compOpt
 
         if (isSIMDCFInst)
         {
-            firstMov->setOptions((inst->getOption() & ~InstOpt_Masks) | InstOpt_WriteEnable);
+            firstMov->setNoMask(true);
         }
     }
 
@@ -1634,11 +1634,11 @@ void HWConformity::saveDst( INST_LIST_ITER& it, uint8_t stride, G4_BB *bb )
     unsigned int new_option = inst->getOption();
 
     G4_INST* newInst = builder.createMov(execSize, tmpDstOpnd, srcRegion, new_option, false);
-    if( bb->isInSimdFlow() )
+    if (bb->isInSimdFlow())
     {
-        newInst->setOptions( ( inst->getOption() & ~InstOpt_Masks ) | InstOpt_WriteEnable );
+        newInst->setNoMask(true);
     }
-    bb->insert( it, newInst );
+    bb->insert(it, newInst);
     inst->setDest(builder.duplicateOperand( tmpDstOpnd ) );
 }
 
@@ -1658,7 +1658,7 @@ void HWConformity::restoreDst( INST_LIST_ITER& it, G4_DstRegRegion *origDst, G4_
     G4_INST* newInst = builder.createMov(execSize, origDst, srcRegion, new_option, false);
     if (bb->isInSimdFlow())
     {
-        newInst->setOptions((inst->getOption() & ~InstOpt_Masks) | InstOpt_WriteEnable);
+        newInst->setNoMask(true);
     }
     INST_LIST_ITER iter = it;
     iter++;
diff --git a/visa/TranslationInterface.cpp b/visa/TranslationInterface.cpp
@@ -1985,7 +1985,7 @@ int IR_Builder::translateVISASyncInst(ISA_Opcode opcode, unsigned int mask)
                 G4_DstRegRegion* dstOpnd = createDst(getBuiltinR0()->getRegVar(), 0, 0, 1, Type_UD);
 
                 G4_INST* nop = createMov(1, dstOpnd, srcOpnd, InstOpt_NoOpt, true);
-                nop->setOptions(nop->getOption() | InstOpt_Switch);
+                nop->setOptionOn(InstOpt_Switch);
             }
         }
         break;
@@ -7634,8 +7634,8 @@ int IR_Builder::translateVISAURBWrite3DInst(
         // shl (8) M2.0<1>:ud cmask<8;8,1>:ud 0x10:uw
         auto payloadUDRegRgnRow2 = createDst(payloadUD->getRegVar(), regOff++, 0, 1, Type_UD);
 
-        G4_INST* channelMaskInst = createInst(nullptr, G4_shl, nullptr, false, 8, payloadUDRegRgnRow2, channelMask, createImm(16, Type_UW), 0);
-        channelMaskInst->setOptionOn( instOpt );
+        createInst(nullptr, G4_shl, nullptr, false, 8, payloadUDRegRgnRow2, channelMask, createImm(16, Type_UW),
+            instOpt);
     }
 
     G4_Declare* vertexDataDcl = numOut == 0 ? NULL : vertexData->getBase()->asRegVar()->getDeclare();
@@ -7653,8 +7653,7 @@ int IR_Builder::translateVISAURBWrite3DInst(
 
             G4_SrcRegRegion* vertexSrcRegRgnRowi = createSrcRegRegion(Mod_src_undef, Direct, vertexDataDcl->getRegVar(), startSrcRow++, 0, getRegionStride1(), Type_F);
 
-            G4_INST* vertexDataMovInst = createMov( 8, payloadTypedRegRowRgni, vertexSrcRegRgnRowi, InstOpt_NoOpt, true );
-            vertexDataMovInst->setOptionOn( instOpt );
+            createMov( 8, payloadTypedRegRowRgni, vertexSrcRegRgnRowi, instOpt, true );
         }
     }
     else
@@ -10795,8 +10794,7 @@ void IR_Builder::Copy_SrcRegRegion_To_Payload( G4_Declare* payload, unsigned int
 
     G4_SrcRegRegion* srcRgn = createSrcRegRegion( *src );
     srcRgn->setType( payload->getElemType() );
-    G4_INST* refCopy = createMov(exec_size, payloadDstRgn, srcRgn, InstOpt_NoOpt, true );
-    refCopy->setOptionOn(emask);
+    createMov(exec_size, payloadDstRgn, srcRgn, emask, true );
     if (G4_Type_Table[payload->getElemType()].byteSize == 2)
     {
         // for half float each source occupies 1 GRF regardless of execution size
diff --git a/visa/ifcvt.cpp b/visa/ifcvt.cpp
@@ -125,30 +125,10 @@ namespace {
         }
 
         /// getEMaskBits() -
-        unsigned getEMaskBits(unsigned maskOpt, unsigned execSize) const {
+        unsigned getEMaskBits(unsigned maskOffset, unsigned execSize) const
+        {
             uint64_t Val = ((uint64_t)1 << execSize) - 1;
-            switch (maskOpt) {
-            case InstOpt_NoOpt:
-                return unsigned(Val);
-            case InstOpt_M0:
-                return unsigned(Val << 0);
-            case InstOpt_M4:
-                return unsigned(Val << 4);
-            case InstOpt_M8:
-                return unsigned(Val<< 8);
-            case InstOpt_M12:
-                return unsigned(Val << 12);
-            case InstOpt_M16:
-                return unsigned(Val << 16);
-            case InstOpt_M20:
-                return unsigned(Val << 20);
-            case InstOpt_M24:
-                return unsigned(Val << 24);
-            case InstOpt_M28:
-                return unsigned(Val << 28);
-            }
-            ASSERT_USER(false, "Invalid mask option!");
-            return 0;
+            return (uint32_t) (Val << maskOffset);
         }
 
         /// getnnerMostIf - If the given BB is the head of an innermost IF
@@ -317,10 +297,9 @@ namespace {
                         "Unexpected 'NoMask' in 'if' emask.");
 
             unsigned maskBits =
-                getEMaskBits(maskOpt & InstOpt_QuarterMasks, I->getExecSize());
+                getEMaskBits(I->getMaskOffset(), I->getExecSize());
             unsigned ifMaskBits =
-                getEMaskBits(ifMaskOpt & InstOpt_QuarterMasks,
-                             ifInst->getExecSize());
+                getEMaskBits(ifInst->getMaskOffset(), ifInst->getExecSize());
             // Skip if emask bits in 'if' cannot cover the one from the given
             // instruction.
             if ((~ifMaskBits) & maskBits)

Original file line number	Diff line number	Diff line change
`@@ -658,8 +658,9 @@ void BinaryEncodingIGA::DoAll()`
`658`	`658`	`nullptr, G4_nop, nullptr, false, 1, nullptr, nullptr, nullptr, InstOpt_NoCompact));`
`659`	`659`	`}`
`660`	`660`	`// set all instruction to be NoCompact`
`661`		`- for (auto inst : *first_bb) {`
`662`		`- inst->setOptions(inst->getOption() \| InstOpt_NoCompact);`
	`661`	`+ for (auto inst : *first_bb)`
	`662`	`+ {`
	`663`	`+ inst->setOptionOn(InstOpt_NoCompact);`
`663`	`664`	`}`
`664`	`665`	`}`
`665`	`666`
Original file line number	Diff line number	Diff line change
`@@ -1118,7 +1118,13 @@ uint16_t G4_INST::getMaskOffset() const`
`1118`	`1118`	`{`
`1119`	`1119`	`unsigned maskOption = (this->getOption() & InstOpt_QuarterMasks);`
`1120`	`1120`
`1121`		`- switch(maskOption)`
	`1121`	`+ if (!builder.hasNibCtrl())`
	`1122`	`+ {`
	`1123`	`+ assert(maskOption != InstOpt_M4 && maskOption != InstOpt_M12 && maskOption != InstOpt_M20 &&`
	`1124`	`+ maskOption != InstOpt_M28 && "nibCtrl is not supported on this platform");`
	`1125`	`+ }`
	`1126`	`+`
	`1127`	`+ switch (maskOption)`
`1122`	`1128`	`{`
`1123`	`1129`	`case InstOpt_NoOpt:`
`1124`	`1130`	`return 0;`
`@@ -1139,7 +1145,7 @@ uint16_t G4_INST::getMaskOffset() const`
`1139`	`1145`	`case InstOpt_M28:`
`1140`	`1146`	`return 28;`
`1141`	`1147`	`default:`
`1142`		`- MUST_BE_TRUE( 0, "Incorrect instruction execution mask" );`
	`1148`	`+ MUST_BE_TRUE(0, "Incorrect instruction execution mask");`
`1143`	`1149`	`return 0;`
`1144`	`1150`	`}`
`1145`	`1151`	`}`
Original file line number	Diff line number	Diff line change
`@@ -207,10 +207,10 @@ G4_DstRegRegion* HWConformity::insertMovAfter( INST_LIST_ITER& it, G4_DstRegRegi`
`207`	`207`	`inst->setSaturate(false);`
`208`	`208`	`}`
`209`	`209`
`210`		`- inst->setExecSize( newExecSize );`
	`210`	`+ inst->setExecSize(newExecSize);`
`211`	`211`	`if (newExecSize == 1)`
`212`	`212`	`{`
`213`		`- inst->setOptions((inst->getOption() & ~InstOpt_Masks ) \| InstOpt_WriteEnable);`
	`213`	`+ inst->setNoMask(true);`
`214`	`214`	`}`
`215`	`215`
`216`	`216`	`return builder.Create_Dst_Opnd_From_Dcl( dcl, scale);`
`@@ -945,7 +945,7 @@ bool HWConformity::fixLine(INST_LIST_ITER it, G4_BB *bb)`
`945`	`945`	`G4_INST* newInst = builder.createMov(mov_size, new_dst_opnd, src0, InstOpt_NoOpt, false);`
`946`	`946`	`if (bb->isInSimdFlow())`
`947`	`947`	`{`
`948`		`- newInst->setOptions((newInst->getOption() & ~InstOpt_Masks) \| InstOpt_WriteEnable);`
	`948`	`+ newInst->setNoMask(true);`
`949`	`949`	`}`
`950`	`950`	`bb->insert(it, newInst);`
`951`	`951`	`inst->setSrc(new_src0_opnd, 0);`
`@@ -2322,7 +2322,7 @@ bool HWConformity::fixMULInst( INST_LIST_ITER &i, G4_BB *bb )`
`2322`	`2322`
`2323`	`2323`	`if (bb->isInSimdFlow())`
`2324`	`2324`	`{`
`2325`		`- inst->setOptions((inst->getOption() & ~InstOpt_Masks) \| InstOpt_WriteEnable);`
	`2325`	`+ inst->setNoMask(true);`
`2326`	`2326`	`}`
`2327`	`2327`
`2328`	`2328`	`if (pred != NULL) {`
`@@ -2663,7 +2663,7 @@ void HWConformity::fixMULHInst( INST_LIST_ITER &i, G4_BB *bb )`
`2663`	`2663`
`2664`	`2664`	`if (bb->isInSimdFlow())`
`2665`	`2665`	`{`
`2666`		`- newMul->setOptions( ( inst_opt & ~InstOpt_Masks ) \| InstOpt_WriteEnable );`
	`2666`	`+ newMul->setNoMask(true);`
`2667`	`2667`	`}`
`2668`	`2668`	`inst->setOpcode( G4_mach );`
`2669`	`2669`
Original file line number	Diff line number	Diff line change
`@@ -6795,7 +6795,7 @@ bool Optimizer::foldPseudoAndOr(G4_BB* bb, INST_LIST_ITER& ii)`
`6795`	`6795`	`inst->isSplitSend() &&`
`6796`	`6796`	`!(inst->getSrc(1)->isNullReg()))`
`6797`	`6797`	`{`
`6798`		`- inst->setOptions(inst->getOption() \| InstOpt_NoPreempt);`
	`6798`	`+ inst->setOptionOn(InstOpt_NoPreempt);`
`6799`	`6799`	`}`
`6800`	`6800`
`6801`	`6801`	`if (inst->isSend() && !inst->isNoPreemptInst() && builder.needsNoPreemptR2ForSend())`
`@@ -6806,7 +6806,7 @@ bool Optimizer::foldPseudoAndOr(G4_BB* bb, INST_LIST_ITER& ii)`
`6806`	`6806`	`unsigned LB = Src0->getLinearizedStart();`
`6807`	`6807`	`if (LB == 2 * GENX_GRF_REG_SIZ)`
`6808`	`6808`	`{`
`6809`		`- inst->setOptions(inst->getOption() \| InstOpt_NoPreempt);`
	`6809`	`+ inst->setOptionOn(InstOpt_NoPreempt);`
`6810`	`6810`	`}`
`6811`	`6811`	`}`
`6812`	`6812`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1048,7 +1048,7 @@ void HWConformity::splitInstruction(INST_LIST_ITER iter, G4_BB* bb, bool compOpt`
`1048`	`1048`
`1049`	`1049`	`if (isSIMDCFInst)`
`1050`	`1050`	`{`
`1051`		`- firstMov->setOptions((inst->getOption() & ~InstOpt_Masks) \| InstOpt_WriteEnable);`
	`1051`	`+ firstMov->setNoMask(true);`
`1052`	`1052`	`}`
`1053`	`1053`	`}`
`1054`	`1054`
`@@ -1634,11 +1634,11 @@ void HWConformity::saveDst( INST_LIST_ITER& it, uint8_t stride, G4_BB *bb )`
`1634`	`1634`	`unsigned int new_option = inst->getOption();`
`1635`	`1635`
`1636`	`1636`	`G4_INST* newInst = builder.createMov(execSize, tmpDstOpnd, srcRegion, new_option, false);`
`1637`		`- if( bb->isInSimdFlow() )`
	`1637`	`+ if (bb->isInSimdFlow())`
`1638`	`1638`	`{`
`1639`		`- newInst->setOptions( ( inst->getOption() & ~InstOpt_Masks ) \| InstOpt_WriteEnable );`
	`1639`	`+ newInst->setNoMask(true);`
`1640`	`1640`	`}`
`1641`		`- bb->insert( it, newInst );`
	`1641`	`+ bb->insert(it, newInst);`
`1642`	`1642`	`inst->setDest(builder.duplicateOperand( tmpDstOpnd ) );`
`1643`	`1643`	`}`
`1644`	`1644`
`@@ -1658,7 +1658,7 @@ void HWConformity::restoreDst( INST_LIST_ITER& it, G4_DstRegRegion *origDst, G4_`
`1658`	`1658`	`G4_INST* newInst = builder.createMov(execSize, origDst, srcRegion, new_option, false);`
`1659`	`1659`	`if (bb->isInSimdFlow())`
`1660`	`1660`	`{`
`1661`		`- newInst->setOptions((inst->getOption() & ~InstOpt_Masks) \| InstOpt_WriteEnable);`
	`1661`	`+ newInst->setNoMask(true);`
`1662`	`1662`	`}`
`1663`	`1663`	`INST_LIST_ITER iter = it;`
`1664`	`1664`	`iter++;`
Original file line number	Diff line number	Diff line change
`@@ -1985,7 +1985,7 @@ int IR_Builder::translateVISASyncInst(ISA_Opcode opcode, unsigned int mask)`
`1985`	`1985`	`G4_DstRegRegion* dstOpnd = createDst(getBuiltinR0()->getRegVar(), 0, 0, 1, Type_UD);`
`1986`	`1986`
`1987`	`1987`	`G4_INST* nop = createMov(1, dstOpnd, srcOpnd, InstOpt_NoOpt, true);`
`1988`		`- nop->setOptions(nop->getOption() \| InstOpt_Switch);`
	`1988`	`+ nop->setOptionOn(InstOpt_Switch);`
`1989`	`1989`	`}`
`1990`	`1990`	`}`
`1991`	`1991`	`break;`
`@@ -7634,8 +7634,8 @@ int IR_Builder::translateVISAURBWrite3DInst(`
`7634`	`7634`	`// shl (8) M2.0<1>:ud cmask<8;8,1>:ud 0x10:uw`
`7635`	`7635`	`auto payloadUDRegRgnRow2 = createDst(payloadUD->getRegVar(), regOff++, 0, 1, Type_UD);`
`7636`	`7636`
`7637`		`- G4_INST* channelMaskInst = createInst(nullptr, G4_shl, nullptr, false, 8, payloadUDRegRgnRow2, channelMask, createImm(16, Type_UW), 0);`
`7638`		`- channelMaskInst->setOptionOn( instOpt );`
	`7637`	`+ createInst(nullptr, G4_shl, nullptr, false, 8, payloadUDRegRgnRow2, channelMask, createImm(16, Type_UW),`
	`7638`	`+ instOpt);`
`7639`	`7639`	`}`
`7640`	`7640`
`7641`	`7641`	`G4_Declare* vertexDataDcl = numOut == 0 ? NULL : vertexData->getBase()->asRegVar()->getDeclare();`
`@@ -7653,8 +7653,7 @@ int IR_Builder::translateVISAURBWrite3DInst(`
`7653`	`7653`
`7654`	`7654`	`G4_SrcRegRegion* vertexSrcRegRgnRowi = createSrcRegRegion(Mod_src_undef, Direct, vertexDataDcl->getRegVar(), startSrcRow++, 0, getRegionStride1(), Type_F);`
`7655`	`7655`
`7656`		`- G4_INST* vertexDataMovInst = createMov( 8, payloadTypedRegRowRgni, vertexSrcRegRgnRowi, InstOpt_NoOpt, true );`
`7657`		`- vertexDataMovInst->setOptionOn( instOpt );`
	`7656`	`+ createMov( 8, payloadTypedRegRowRgni, vertexSrcRegRgnRowi, instOpt, true );`
`7658`	`7657`	`}`
`7659`	`7658`	`}`
`7660`	`7659`	`else`
`@@ -10795,8 +10794,7 @@ void IR_Builder::Copy_SrcRegRegion_To_Payload( G4_Declare* payload, unsigned int`
`10795`	`10794`
`10796`	`10795`	`G4_SrcRegRegion* srcRgn = createSrcRegRegion( *src );`
`10797`	`10796`	`srcRgn->setType( payload->getElemType() );`
`10798`		`- G4_INST* refCopy = createMov(exec_size, payloadDstRgn, srcRgn, InstOpt_NoOpt, true );`
`10799`		`- refCopy->setOptionOn(emask);`
	`10797`	`+ createMov(exec_size, payloadDstRgn, srcRgn, emask, true );`
`10800`	`10798`	`if (G4_Type_Table[payload->getElemType()].byteSize == 2)`
`10801`	`10799`	`{`
`10802`	`10800`	`// for half float each source occupies 1 GRF regardless of execution size`