Fix kernel attributes processing

Change-Id: If9cf1d2ab92c875e2b6f51d75751d09722b41ae8

Author: zuban32

visa/BuildCISAIRImpl.cpp

@@ -886,6 +886,7 @@ int CISA_IR_Builder::Compile(const char* nameInput, std::ostream* os, bool emit_
         for( iter = m_kernels.begin(), i = 0; iter != end; iter++, i++ )
         {
             VISAKernelImpl* kernel = (*iter);
+            kernel->processAttributes();
             kernel->getIRBuilder()->setIsKernel(kernel->getIsKernel());
             kernel->getIRBuilder()->setCUnitId(i);
             if( kernel->getIsKernel() == false )

visa/BuildIR.h

@@ -875,13 +875,13 @@ class IR_Builder {
     void initBuiltinSLMSpillAddr(int perThreadSLMSize);
 
     IR_Builder(INST_LIST_NODE_ALLOCATOR &alloc, PhyRegPool &pregs, G4_Kernel &k,
-        Mem_Manager &m, Options *options, bool isFESP64Bits,
+        Mem_Manager &m, Options *options,
         FINALIZER_INFO *jitInfo = NULL, PVISA_WA_TABLE pWaTable = NULL)
         : curFile(NULL), curLine(0), curCISAOffset(-1), immPool(*this), func_id(-1), metaData(jitInfo),
         isKernel(false), cunit(0),
         builtinSamplerHeaderInitialized(false), m_pWaTable(pWaTable), m_options(options), CanonicalRegionStride0(0, 1, 0),
         CanonicalRegionStride1(1, 1, 0), CanonicalRegionStride2(2, 1, 0), CanonicalRegionStride4(4, 1, 0),
-        use64BitFEStackVars(isFESP64Bits), mem(m), phyregpool(pregs), hashtable(m), rgnpool(m), dclpool(m),
+        use64BitFEStackVars(false), mem(m), phyregpool(pregs), hashtable(m), rgnpool(m), dclpool(m),
         instList(alloc), kernel(k)
     {
         num_general_dcl = 0;

visa/VISAKernel.h

@@ -230,6 +230,8 @@ class VISAKernelImpl : public VISAFunction
 
     int getVISAOffset() const;
 
+    void processAttributes();
+
     /***************** START EXPOSED APIS *************************/
     VISA_BUILDER_API int CreateVISAGenVar(VISA_GenVar *& decl, const char *varName, int numberElements, VISA_Type dataType,
         VISA_Align varAlign, VISA_GenVar *parentDecl = NULL, int aliasOffset = 0);

visa/VISAKernelImpl.cpp

@@ -456,27 +456,12 @@ int VISAKernelImpl::InitializeFastPath()
     }
     m_jitInfo = (FINALIZER_INFO*)m_mem.alloc(sizeof(FINALIZER_INFO));
 
-    int feSPSize = 32;
-    if (!getIntKernelAttributeValue("FESPSize", feSPSize))
-    {
-        feSPSize = 32;
-    }
-    int spillMemOffset = 0;
-    if (getIntKernelAttributeValue("SpillMemOffset", spillMemOffset))
-    {
-        if (spillMemOffset > 0)
-        {
-            getOptions()->setOption(vISA_SpillMemOffset, (uint32_t)spillMemOffset);
-        }
-    }
-
     void* addr = m_kernelMem->alloc(sizeof(class IR_Builder));
     m_builder = new(addr)IR_Builder(m_instListNodeAllocator,
         *m_phyRegPool,
         *m_kernel,
         *m_kernelMem,
         m_options,
-        (feSPSize == 64),
         m_jitInfo,
         m_pWaTable
         );
@@ -8148,6 +8133,23 @@ int VISAKernelImpl::getVISAOffset() const
     return -1;
 }
 
+void VISAKernelImpl::processAttributes()
+{
+  int feSPSize = 32;
+  if (getIntKernelAttributeValue("FESPSize", feSPSize) && feSPSize == 64)
+  {
+    m_builder->set64BitFEStackVars();
+  }
+  int spillMemOffset = 0;
+  if (getIntKernelAttributeValue("SpillMemOffset", spillMemOffset))
+  {
+    if (spillMemOffset > 0)
+    {
+      getOptions()->setOption(vISA_SpillMemOffset, (uint32_t)spillMemOffset);
+    }
+  }
+}
+
 void VISAKernelImpl::computeFCInfo(BinaryEncodingBase* binEncodingInstance)
 {
     // This function iterates over all instructions in kernel and sets up data