Emit null register sources for typed lsc operations in VC

When the typed lsc messages have some of the texture coordinates being
equal to zero, the register sources for such coordinates can be omitted
to reduce the register pressure.

Author: vmustya

IGC/VectorCompiler/lib/GenXCodeGen/GenXPatternMatch.cpp

@@ -202,6 +202,7 @@ class GenXPatternMatch : public FunctionPass,
   bool simplifyCmp(CmpInst *Cmp);
   CmpInst *reduceCmpWidth(CmpInst *Cmp);
   bool simplifyNullDst(CallInst *Inst);
+  bool simplifyNullSrc(CallInst *Inst);
   bool simplifyDpasNullSrc(CallInst *Inst);
   // Transform logic operation with a mask from <N x iM> to <N/(32/M) x i32>
   bool extendMask(BinaryOperator *BO);
@@ -819,7 +820,7 @@ void GenXPatternMatch::visitBinaryOperator(BinaryOperator &I) {
 }
 
 void GenXPatternMatch::visitCallInst(CallInst &I) {
-  if (I.use_empty())
+  if (I.use_empty() && !I.getType()->isVoidTy())
     return;
 
   auto IID = vc::getAnyIntrinsicID(&I);
@@ -864,6 +865,15 @@ void GenXPatternMatch::visitCallInst(CallInst &I) {
   case GenXIntrinsic::genx_uutrunc_sat:
     Changed |= simplifyTruncSat(&I);
     break;
+
+  case vc::InternalIntrinsic::lsc_load_quad_tgm:
+    Changed |= simplifyNullDst(&I);
+    LLVM_FALLTHROUGH;
+  case vc::InternalIntrinsic::lsc_prefetch_quad_tgm:
+  case vc::InternalIntrinsic::lsc_store_quad_tgm:
+    Changed |= simplifyNullSrc(&I);
+    break;
+
   case vc::InternalIntrinsic::lsc_atomic_ugm:
   case vc::InternalIntrinsic::lsc_load_ugm:
   case vc::InternalIntrinsic::lsc_load_quad_ugm:
@@ -883,7 +893,6 @@ void GenXPatternMatch::visitCallInst(CallInst &I) {
   case vc::InternalIntrinsic::lsc_load_quad_slm:
   case vc::InternalIntrinsic::lsc_store_slm:
   case vc::InternalIntrinsic::lsc_store_quad_slm:
-  case vc::InternalIntrinsic::lsc_load_quad_tgm:
   case GenXIntrinsic::genx_dword_atomic_fadd:
   case GenXIntrinsic::genx_dword_atomic_fsub:
   case GenXIntrinsic::genx_dword_atomic_add:
@@ -4285,6 +4294,31 @@ bool GenXPatternMatch::simplifyNullDst(CallInst *Inst) {
   return false;
 }
 
+bool GenXPatternMatch::simplifyNullSrc(CallInst *Inst) {
+  if (!vc::InternalIntrinsic::isInternalMemoryIntrinsic(Inst))
+    return false;
+
+  bool Changed = false;
+
+  auto IID = vc::getAnyIntrinsicID(Inst);
+  GenXIntrinsicInfo Info(IID);
+
+  for (unsigned I = 0; I < Inst->arg_size(); ++I) {
+    auto *Arg = dyn_cast<Constant>(Inst->getArgOperand(I));
+    if (!Arg || !Arg->isNullValue())
+      continue;
+
+    auto ArgInfo = Info.getArgInfo(I);
+    if (!ArgInfo.isRaw() || !ArgInfo.isNullAllowed())
+      continue;
+
+    Inst->setArgOperand(I, UndefValue::get(Arg->getType()));
+    Changed = true;
+  }
+
+  return Changed;
+}
+
 bool GenXPatternMatch::simplifyDpasNullSrc(CallInst *Inst) {
   if (ST->hasFusedEU())
     return false;

IGC/VectorCompiler/test/PatternMatch/tgm-null-src.ll

@@ -0,0 +1,26 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; RUN: %opt %use_old_pass_manager% -GenXPatternMatch -march=genx64 -mcpu=Xe2 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s
+
+declare <64 x float> @llvm.vc.internal.lsc.load.quad.tgm.v64f32.v32i1.v2i8.v32i32(<32 x i1>, <2 x i8>, i8, i32, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <64 x float>)
+declare void @llvm.vc.internal.lsc.store.quad.tgm.v32i1.v2i8.v32i32.v64f32(<32 x i1>, <2 x i8>, i8, i32, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <64 x float>)
+declare void @llvm.vc.internal.lsc.prefetch.quad.tgm.v32i1.v2i8.v32i32(<32 x i1>, <2 x i8>, i8, i32, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>)
+
+define void @test(i32 %bti, <32 x i32> %u, <32 x i32> %v) {
+  ; CHECK: tail call void @llvm.vc.internal.lsc.prefetch.quad.tgm.v32i1.v2i8.v32i32(<32 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <2 x i8> zeroinitializer, i8 3, i32 %bti, <32 x i32> %u, <32 x i32> %v, <32 x i32> undef, <32 x i32> undef)
+  tail call void @llvm.vc.internal.lsc.prefetch.quad.tgm.v32i1.v2i8.v32i32(<32 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <2 x i8> zeroinitializer, i8 3, i32 %bti, <32 x i32> %u, <32 x i32> %v, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer)
+
+  ; CHECK: %load = tail call <64 x float> @llvm.vc.internal.lsc.load.quad.tgm.v64f32.v32i1.v2i8.v32i32(<32 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <2 x i8> zeroinitializer, i8 3, i32 %bti, <32 x i32> %u, <32 x i32> %v, <32 x i32> undef, <32 x i32> undef, <64 x float> undef)
+  %load = tail call <64 x float> @llvm.vc.internal.lsc.load.quad.tgm.v64f32.v32i1.v2i8.v32i32(<32 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <2 x i8> zeroinitializer, i8 3, i32 %bti, <32 x i32> %u, <32 x i32> %v, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, <64 x float> undef)
+
+  ; CHECK: tail call void @llvm.vc.internal.lsc.store.quad.tgm.v32i1.v2i8.v32i32.v64f32(<32 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <2 x i8> zeroinitializer, i8 3, i32 %bti, <32 x i32> %u, <32 x i32> %v, <32 x i32> undef, <32 x i32> undef, <64 x float> %load)
+  tail call void @llvm.vc.internal.lsc.store.quad.tgm.v32i1.v2i8.v32i32.v64f32(<32 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <2 x i8> zeroinitializer, i8 3, i32 %bti, <32 x i32> %u, <32 x i32> %v, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, <64 x float> %load)
+
+  ret void
+}