Enable NULL render target feature for RTW messages

Change-Id: I07cb98ebbafcf314750b95ca72be4277501337ed

Author: fangliu2020

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -2471,6 +2471,9 @@ namespace IGC
         //controls last render target select bit
         cntrls.isLastWrite = lastRenderTarget;
 
+        // controls NULL render target enbale bit
+        cntrls.isNullRT = false;
+
         //r1Reg should always be populated
         //vISA will decide whether to use it or not.
         VISA_RawOpnd* r1RegOpnd = GetRawSource(r1Reg);

visa/BuildCISAIRImpl.cpp

@@ -2229,6 +2229,11 @@ bool CISA_IR_Builder::CISA_create_rtwrite_3d_instruction(
         {
             cntrls.isCoarseMode = true;
         }
+
+        if (strstr(mode, "NULLRT"))
+        {
+            cntrls.isNullRT = true;
+        }
     }
     else
     {

visa/ByteCodeReaderNG.cpp

@@ -948,6 +948,7 @@ static void readInstructionDataportNG(unsigned& bytePos, const char* buf, ISA_Op
             cntrls.isCoarseMode  = (mode & (0x1 << 10))? true:false;
             cntrls.isSampleIndex = (mode & (0x1 << 11)) ? true : false;
             cntrls.RTIndexPresent = (mode & (0x1 << 2)) ? true : false;
+            cntrls.isNullRT = (mode & (0x1 << 12)) ? true : false;
             cntrls.isHeaderMaskfromCe0 = 0;
 
             VISA_VectorOpnd *sampleIndex = cntrls.isSampleIndex ? readVectorOperandNG(bytePos, buf, container, false) : NULL;

visa/Gen4_IR.hpp

@@ -345,7 +345,7 @@ class G4_SendMsgDescriptor
         return createExtDesc(funcID, isEot, 0, 0);
     }
 
-    static uint32_t createMRTExtDesc(bool src0Alpha, uint8_t RTIndex, bool isEOT, uint32_t extMsgLen)
+    static uint32_t createMRTExtDesc(bool src0Alpha, uint8_t RTIndex, bool isEOT, uint32_t extMsgLen, uint16_t extFuncCtrl)
     {
         ExtDescData data;
         data.value = 0;
@@ -354,6 +354,7 @@ class G4_SendMsgDescriptor
         data.layout.src0Alpha = src0Alpha;
         data.layout.eot = isEOT;
         data.layout.extMsgLength = extMsgLen;
+        data.layout.extFuncCtrl = extFuncCtrl;
         return data.value;
     }
 

visa/IsaDisassembly.cpp

@@ -2392,6 +2392,7 @@ static std::string printInstructionDataport(
                 if( mode & (0x1 << 0x9)) sstr << "<PS>";
                 if( mode & (0x1 << 0x10)) sstr << "<CM>";
                 if (mode & (0x1 << 0x11)) sstr << "<SI>";
+                if (mode & (0x1 << 0x12)) sstr << "<NULLRT>";
             }
 
             sstr << " " << printExecutionSize(inst->opcode, inst->execsize) << " ";

visa/TranslationInterface.cpp

@@ -8294,6 +8294,16 @@ int IR_Builder::translateVISARTWrite3DInst(
     if(cntrls.isCoarseMode)
             fc |= 0x1 << COARSE_PIXEL_OUTPUT_ENABLE;
 #define CPS_COUNTER_EXT_MSG_DESC_OFFSET 16
+
+    uint16_t extFuncCtrl = 0;
+    if (cntrls.isNullRT && getPlatform() >= GENX_ICLLP)
+    {
+        // extFuncCtrl is the 16:31 bits of extDesc. NullRT is the bit 20 of extDesc.
+        // That says NullRT is the bit 4 of extFuncCtrl.
+#define NULL_RENDER_TARGET 4
+        extFuncCtrl |= 0x1 << NULL_RENDER_TARGET;
+    }
+
     if (useSplitSend || cpsCounter)
     {
         G4_SendMsgDescriptor *msgDesc = NULL;
@@ -8303,7 +8313,7 @@ int IR_Builder::translateVISARTWrite3DInst(
         {
             m0 = Create_Src_Opnd_From_Dcl(msg, getRegionStride1());
             msgDesc = createSendMsgDesc(fc, 0, numHeaderGRF, SFID::DP_WRITE, numRows,
-                0, SendAccess::WRITE_ONLY, surface);
+                extFuncCtrl, SendAccess::WRITE_ONLY, surface);
             msgDesc->setHeaderPresent(useHeader);
         }
         else
@@ -8312,16 +8322,15 @@ int IR_Builder::translateVISARTWrite3DInst(
             {
                 // direct imm is a-ok for ext desc
                 msgDesc = createSendMsgDesc(fc, 0, numRows, SFID::DP_WRITE, 0,
-                        0, SendAccess::WRITE_ONLY, surface);
+                    extFuncCtrl, SendAccess::WRITE_ONLY, surface);
             }
             else
             {
-
                 assert(rtIndex->isImm() && "RTIndex must be imm at this point");
                 uint8_t RTIndex = (uint8_t)rtIndex->asImm()->getImm() & 0x7;
                 uint32_t desc = G4_SendMsgDescriptor::createDesc(fc, false, numRows, 0);
                 uint32_t extDesc = G4_SendMsgDescriptor::createMRTExtDesc(cntrls.s0aPresent, RTIndex,
-                    false, 0);
+                    false, 0, extFuncCtrl);
                 msgDesc = createGeneralMsgDesc(desc, extDesc, SendAccess::WRITE_ONLY, surface);
 
                 if (!canEncodeFullExtDesc())

visa/VISAKernelImpl.cpp

@@ -5674,16 +5674,17 @@ int VISAKernelImpl::AppendVISA3dRTWriteCPS(VISA_PredOpnd *pred, VISA_EMask_Ctrl
         int num_operands = 0;
         bool isCPSCounter = (cPSCounter)? true: false;
 
-        int mode =  ((int)cntrls.isSampleIndex << 11)  |
+        int mode =  ((int)cntrls.isNullRT      << 12)   |
+                    ((int)cntrls.isSampleIndex << 11)   |
                     ((int)cntrls.isCoarseMode   << 10)  |
                     ((int)cntrls.isPerSample    << 9)   |
                     ((int)(isCPSCounter)        << 8)   |
-                    (((int)cntrls.isLastWrite   << 7)   |
+                    ((int)cntrls.isLastWrite    << 7)   |
                     ((int)cntrls.isStencil      << 6)   |
                     ((int)cntrls.zPresent       << 5)   |
                     ((int)cntrls.oMPresent      << 4)   |
                     ((int)cntrls.s0aPresent     << 3)   |
-                    ((int)cntrls.RTIndexPresent << 2));
+                    ((int)cntrls.RTIndexPresent << 2);
 
         //mode
         ADD_OPND(num_operands, opnd, this->CreateOtherOpndHelper(num_pred_desc_operands, num_operands, inst_desc, mode));

visa/include/visa_igc_common_header.h

@@ -621,6 +621,7 @@ typedef struct _vISA_RT_CONTROLS
     unsigned isCoarseMode:1; //controls coasrse mode bit inmsg descriptor
     unsigned isSampleIndex : 1; //controls whether sampleIndex is used.
     unsigned isHeaderMaskfromCe0 : 1;
+    unsigned isNullRT : 1;   // null render target
 } vISA_RT_CONTROLS;
 
 typedef enum