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pratikasharigcbot
pratikashar
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igcbot
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Changes in code.
1 parent a016d32 commit 50889f3

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+75
-79
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2 files changed

+75
-79
lines changed

‎IGC/DebugInfo/DwarfDebug.cpp‎

Lines changed: 75 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -2924,7 +2924,7 @@ uint32_t DwarfDebug::writeStackcallCIE() {
29242924
// return address register - uleb128
29252925
// set machine return register to one which is physically
29262926
// absent. later CFA instructions map this to a valid GRF.
2927-
writeULEB128(data, RegisterNumbering::IP);
2927+
writeULEB128(data, GetEncodedRegNum<RegisterNumbering::GRFBase>(numGRFs));
29282928

29292929
// initial instructions (array of ubyte)
29302930
// DW_OP_regx r125
@@ -2933,12 +2933,11 @@ uint32_t DwarfDebug::writeStackcallCIE() {
29332933

29342934
// The DW_CFA_def_cfa_expression instruction takes a single operand
29352935
// encoded as a DW_FORM_exprloc.
2936-
// We define DW_CFA_def_cfa_expression to point to caller's BE_SP.
29372936
auto DWRegEncoded = GetEncodedRegNum<RegisterNumbering::GRFBase>(specialGRF);
29382937
write(data1, (uint8_t)llvm::dwarf::DW_OP_const4u);
29392938
write(data1, (uint32_t)(DWRegEncoded));
29402939
write(data1, (uint8_t)llvm::dwarf::DW_OP_const2u);
2941-
write(data1, (uint16_t)(getBESPSubReg() * 4 * 8));
2940+
write(data1, (uint16_t)(getBEFPSubReg() * 4 * 8));
29422941
write(data1, (uint8_t)DW_OP_INTEL_regval_bits);
29432942
write(data1, (uint8_t)32);
29442943

@@ -2972,20 +2971,10 @@ uint32_t DwarfDebug::writeStackcallCIE() {
29722971
}
29732972

29742973
// move return address register to actual location
2975-
if (GetABIVersion() < 3) {
2976-
// DW_CFA_register IP specialGRF
2977-
write(data, (uint8_t)llvm::dwarf::DW_CFA_register);
2978-
writeULEB128(data, RegisterNumbering::IP);
2979-
writeULEB128(data,
2980-
GetEncodedRegNum<RegisterNumbering::GRFBase>(specialGRF));
2981-
} else {
2982-
write(data, (uint8_t)llvm::dwarf::DW_CFA_expression);
2983-
writeULEB128(data, RegisterNumbering::IP);
2984-
writeULEB128(data, 6);
2985-
write(data, (uint8_t)llvm::dwarf::DW_OP_const4u);
2986-
write(data, (uint32_t)getRetIPSubReg() * 4);
2987-
write(data, (uint8_t)llvm::dwarf::DW_OP_plus);
2988-
}
2974+
// DW_CFA_register numGRFs specialGRF
2975+
write(data, (uint8_t)llvm::dwarf::DW_CFA_register);
2976+
writeULEB128(data, GetEncodedRegNum<RegisterNumbering::GRFBase>(numGRFs));
2977+
writeULEB128(data, GetEncodedRegNum<RegisterNumbering::GRFBase>(specialGRF));
29892978

29902979
while ((lenSize + data.size()) % ptrSize != 0)
29912980
// Insert DW_CFA_nop
@@ -3114,6 +3103,7 @@ void DwarfDebug::writeFDEStackCall(VISAModule *m) {
31143103
auto sortAsc = [](uint64_t a, uint64_t b) { return a < b; };
31153104
std::map<uint64_t, std::vector<uint8_t>, decltype(sortAsc)> cfaOps(sortAsc);
31163105
const auto &DbgInfo = *VisaDbgInfo;
3106+
auto numGRFs = GetVISAModule()->getNumGRFs();
31173107
auto specialGRF = GetSpecialGRF();
31183108

31193109
auto advanceLoc = [&loc](std::vector<uint8_t> &data, uint64_t newLoc) {
@@ -3134,25 +3124,33 @@ void DwarfDebug::writeFDEStackCall(VISAModule *m) {
31343124
loc = newLoc;
31353125
};
31363126

3137-
// When useBEFP is true, expression refers to BEFP. Otherwise,
3138-
// expression refers to BESP.
3139-
auto writeOffBEStack = [specialGRF, this](std::vector<uint8_t> &data,
3140-
bool useBEFP) {
3141-
// DW_OP_const4u 127
3142-
// DW_OP_const2u BE_FP_SubReg
3143-
// DW_OP_INTEL_regval_bits 32
3144-
// DW_OP_breg6
3127+
// offset to read off be_fp
3128+
// deref - decide whether or not to emit DW_OP_deref
3129+
// normalizeResult - true when reading a value from scratch space that is a
3130+
// scratch space address
3131+
auto writeOffBEFP = [specialGRF, this](std::vector<uint8_t> &data,
3132+
uint32_t offset, bool deref,
3133+
bool normalizeResult) {
3134+
// DW_OP_const1u 12
3135+
// DW_OP_regx 125
3136+
// DW_OP_const2u 96
3137+
// DW_OP_const1u 32
3138+
// DW_OP_INTEL_push_bit_piece_stack
3139+
// DW_OP_const1u 16
3140+
// DW_OP_mul
3141+
// DW_OP_constu <memory offset>
31453142
// DW_OP_plus
3146-
3143+
// DW_OP_constu 0x900000000000000
3144+
// DW_OP_or
3145+
// DW_OP_deref
31473146
std::vector<uint8_t> data1;
31483147

31493148
auto DWRegEncoded =
31503149
GetEncodedRegNum<RegisterNumbering::GRFBase>(specialGRF);
31513150
write(data1, (uint8_t)llvm::dwarf::DW_OP_const4u);
31523151
write(data1, (uint32_t)(DWRegEncoded));
31533152
write(data1, (uint8_t)llvm::dwarf::DW_OP_const2u);
3154-
write(data1,
3155-
(uint16_t)((useBEFP ? getBEFPSubReg() : getBESPSubReg()) * 4 * 8));
3153+
write(data1, (uint16_t)(getBEFPSubReg() * 4 * 8));
31563154
write(data1, (uint8_t)DW_OP_INTEL_regval_bits);
31573155
write(data1, (uint8_t)32);
31583156

@@ -3165,20 +3163,49 @@ void DwarfDebug::writeFDEStackCall(VISAModule *m) {
31653163
write(data1, (uint8_t)llvm::dwarf::DW_OP_mul);
31663164
}
31673165

3166+
write(data1, (uint8_t)llvm::dwarf::DW_OP_constu);
3167+
writeULEB128(data1, offset);
3168+
write(data1, (uint8_t)llvm::dwarf::DW_OP_plus);
3169+
31683170
// indicate that the resulting address is on BE stack
31693171
encodeScratchAddrSpace(data1);
31703172

3173+
if (deref) {
3174+
write(data1, (uint8_t)llvm::dwarf::DW_OP_deref);
3175+
// DW_OP_deref reads as many bytes as size of address on target machine.
3176+
// We set address size to 64 bits in CIE. However, this expression
3177+
// refers to a slot in scratch space which uses 32-bit addressing. So
3178+
// mask upper 32 bits read from VISA frame descriptor.
3179+
write(data1, (uint8_t)llvm::dwarf::DW_OP_const4u);
3180+
write(data1, (uint32_t)0xffffffff);
3181+
write(data1, (uint8_t)llvm::dwarf::DW_OP_and);
3182+
}
3183+
3184+
if (EmitSettings.ScratchOffsetInOW && normalizeResult) {
3185+
// since data stored in scratch space is also in oword units, normalize it
3186+
write(data1, (uint8_t)llvm::dwarf::DW_OP_const1u);
3187+
write(data1, (uint8_t)16);
3188+
write(data1, (uint8_t)llvm::dwarf::DW_OP_mul);
3189+
}
3190+
3191+
if (deref) {
3192+
// DW_OP_deref earlier causes CFA to be put on top of dwarf stack.
3193+
// Indicate that the address space of CFA is scratch.
3194+
encodeScratchAddrSpace(data1);
3195+
}
3196+
31713197
writeULEB128(data, data1.size());
31723198
for (auto item : data1)
31733199
write(data, (uint8_t)item);
31743200
};
31753201

3176-
auto writeLR = [this, writeOffBEStack](
3177-
std::vector<uint8_t> &data,
3178-
const DbgDecoder::LiveIntervalGenISA &lr, bool useBEFP) {
3202+
auto writeLR = [this, writeOffBEFP](std::vector<uint8_t> &data,
3203+
const DbgDecoder::LiveIntervalGenISA &lr,
3204+
bool deref, bool normalizeResult) {
31793205
if (lr.var.physicalType ==
31803206
DbgDecoder::VarAlloc::PhysicalVarType::PhyTypeMemory) {
3181-
writeOffBEStack(data, useBEFP);
3207+
writeOffBEFP(data, (uint32_t)lr.var.mapping.m.memoryOffset, deref,
3208+
normalizeResult);
31823209

31833210
IGC_ASSERT_MESSAGE(!lr.var.mapping.m.isBaseOffBEFP,
31843211
"Expecting location offset from BE_FP");
@@ -3193,23 +3220,6 @@ void DwarfDebug::writeFDEStackCall(VISAModule *m) {
31933220
writeULEB128(data, srcReg);
31943221
};
31953222

3196-
// Caller has written DW_CFA_expression and a register. Here, we
3197-
// emit offset off CFA where the register is stored. For eg,
3198-
// DW_CFA_expression: r143 (DW_OP_const4u: 0; DW_OP_plus)
3199-
//
3200-
// means that r127 is stored at [CFA + 0]
3201-
auto writeCFAExpr = [](std::vector<uint8_t> &data, uint32_t offset) {
3202-
std::vector<uint8_t> data1;
3203-
3204-
write(data1, (uint8_t)llvm::dwarf::DW_OP_const4u);
3205-
write(data1, (uint32_t)offset);
3206-
write(data1, (uint8_t)llvm::dwarf::DW_OP_plus);
3207-
3208-
writeULEB128(data, data1.size());
3209-
for (auto item : data1)
3210-
write(data, (uint8_t)item);
3211-
};
3212-
32133223
auto ptrSize = Asm->GetPointerSize();
32143224
const auto &CFI = DbgInfo.getCFI();
32153225
// Emit CIE
@@ -3248,15 +3258,15 @@ void DwarfDebug::writeFDEStackCall(VISAModule *m) {
32483258
// map out CFA to an offset on be stack
32493259
write(cfaOps[item.start],
32503260
(uint8_t)llvm::dwarf::DW_CFA_def_cfa_expression);
3251-
writeLR(cfaOps[item.start], item, true);
3261+
writeLR(cfaOps[item.start], item, true, true);
32523262
}
32533263

32543264
// describe r125 is at [r125.3]:ud
32553265
auto ip = callerFP.front().start;
32563266
write(cfaOps[ip], (uint8_t)llvm::dwarf::DW_CFA_expression);
32573267
writeULEB128(cfaOps[ip],
32583268
GetEncodedRegNum<RegisterNumbering::GRFBase>(specialGRF));
3259-
writeCFAExpr(cfaOps[ip], 0);
3269+
writeOffBEFP(cfaOps[ip], 0, false, false);
32603270
writeSameValue(cfaOps[callerFP.back().end + MovGenInstSizeInBytes],
32613271
GetEncodedRegNum<RegisterNumbering::GRFBase>(specialGRF));
32623272
}
@@ -3267,8 +3277,9 @@ void DwarfDebug::writeFDEStackCall(VISAModule *m) {
32673277
for (auto &item : retAddr) {
32683278
// start live-range
32693279
write(cfaOps[item.start], (uint8_t)llvm::dwarf::DW_CFA_expression);
3270-
writeULEB128(cfaOps[item.start], RegisterNumbering::IP);
3271-
writeCFAExpr(cfaOps[item.start], getRetIPSubReg() * 4);
3280+
writeULEB128(cfaOps[item.start],
3281+
GetEncodedRegNum<RegisterNumbering::GRFBase>(numGRFs));
3282+
writeLR(cfaOps[item.start], item, false, false);
32723283

32733284
// end live-range
32743285
// VISA emits following:
@@ -3287,14 +3298,20 @@ void DwarfDebug::writeFDEStackCall(VISAModule *m) {
32873298
// offset 656 should we read ret %ip from r125 directly. This is achieved
32883299
// by taking offset 640 reported by VISA debug info and adding 16 to it
32893300
// which is size of the mov instruction.
3290-
writeSameValue(cfaOps[item.end + MovGenInstSizeInBytes],
3291-
RegisterNumbering::IP);
3301+
write(cfaOps[item.end + MovGenInstSizeInBytes],
3302+
(uint8_t)llvm::dwarf::DW_CFA_register);
3303+
writeULEB128(cfaOps[item.end + MovGenInstSizeInBytes],
3304+
GetEncodedRegNum<RegisterNumbering::GRFBase>(numGRFs));
3305+
writeULEB128(
3306+
cfaOps[item.end + MovGenInstSizeInBytes],
3307+
GetEncodedRegNum<RegisterNumbering::GRFBase>(GetSpecialGRF()));
32923308
}
32933309
} else {
32943310
if (m->GetType() == VISAModule::ObjectType::KERNEL) {
32953311
// set return location to be undefined in top frame
32963312
write(cfaOps[0], (uint8_t)llvm::dwarf::DW_CFA_undefined);
3297-
writeULEB128(cfaOps[0], RegisterNumbering::IP);
3313+
writeULEB128(cfaOps[0],
3314+
GetEncodedRegNum<RegisterNumbering::GRFBase>(numGRFs));
32983315
}
32993316
}
33003317

@@ -3313,8 +3330,8 @@ void DwarfDebug::writeFDEStackCall(VISAModule *m) {
33133330
(uint8_t)llvm::dwarf::DW_CFA_expression);
33143331
writeULEB128(cfaOps[item.genIPOffset],
33153332
GetEncodedRegNum<RegisterNumbering::GRFBase>(regNum));
3316-
writeCFAExpr(cfaOps[item.genIPOffset],
3317-
(uint32_t)item.data[idx].dst.m.memoryOffset);
3333+
writeOffBEFP(cfaOps[item.genIPOffset],
3334+
item.data[idx].dst.m.memoryOffset, false, false);
33183335
calleeSaveRegsSaved.insert(regNum);
33193336
} else {
33203337
// already saved, so no need to emit same save again

‎IGC/DebugInfo/DwarfDebug.hpp‎

Lines changed: 0 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -745,27 +745,6 @@ class DwarfDebug {
745745
return BEFPSubReg_3;
746746
}
747747

748-
uint32_t getBESPSubReg() {
749-
auto ver = GetABIVersion();
750-
if (ver < 3)
751-
return BESPSubReg_1_2;
752-
return BESPSubReg_3;
753-
}
754-
755-
uint32_t getRetIPSubReg() {
756-
auto ver = GetABIVersion();
757-
if (ver < 3)
758-
return RetIpSubReg_1_2;
759-
return RetIpSubReg_3;
760-
}
761-
762-
uint32_t RetIpByteSize() {
763-
auto ver = GetABIVersion();
764-
if (ver < 3)
765-
return 4;
766-
return 8;
767-
}
768-
769748
private:
770749
void encodeRange(CompileUnit *TheCU, DIE *ScopeDIE,
771750
const llvm::SmallVectorImpl<InsnRange> *Ranges);

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