Change default SIMD size guess for PVC family

Change PVC SIMD size guess to help with register pressure calculation.

Author: stefan-il

IGC/Compiler/CISACodeGen/IGCLivenessAnalysis.cpp

@@ -57,11 +57,6 @@ SIMDMode IGCLivenessAnalysisBase::bestGuessSIMDSize(Function *F) {
     return SIMDMode::SIMD32;
   }
 
-  auto FG = FGA ? FGA->getGroup(F) : nullptr;
-  bool hasStackCall = (FG && FG->hasStackCall()) || (F && F->hasFnAttribute("visaStackCall"));
-  bool isIndirectGroup = FG && FGA->isIndirectCallGroup(FG);
-  bool hasSubroutine = FG && !FG->isSingle() && !hasStackCall && !isIndirectGroup;
-
   // if we can find metadata with stipulations how we should compile we use it
   if (F && MDUtils->findFunctionsInfoItem(F) != MDUtils->end_FunctionsInfo()) {
     IGC::IGCMD::FunctionInfoMetaDataHandle funcInfoMD = MDUtils->getFunctionsInfoItem(F);
@@ -72,8 +67,15 @@ SIMDMode IGCLivenessAnalysisBase::bestGuessSIMDSize(Function *F) {
 
   // rule for pvc
   if (CGCtx->platform.isProductChildOf(IGFX_PVC)) {
-    if (hasSubroutine)
+    bool abortOnSpills =
+        IGC_GET_FLAG_VALUE(AllowSIMD16DropForXE2Plus) && (CGCtx->platform.isCoreXE2() || CGCtx->platform.isCoreXE3());
+    auto FG = FGA ? FGA->getGroup(F) : nullptr;
+    bool hasStackCall = (FG && FG->hasStackCall()) || (F && F->hasFnAttribute("visaStackCall"));
+    bool isIndirectGroup = FG && FGA->isIndirectCallGroup(FG);
+    bool hasSubroutine = FG && !FG->isSingle() && !hasStackCall && !isIndirectGroup;
+    if (abortOnSpills || hasSubroutine) {
       return SIMDMode::SIMD16;
+    }
     return SIMDMode::SIMD32;
   }
 
@@ -128,7 +130,7 @@ unsigned int IGCLivenessAnalysisBase::addOperandsToSet(llvm::Instruction *Inst,
   if (Phi)
     return 0;
 
-  // do not process debug instructions and lifetimehints in any way
+    // do not process debug instructions and lifetimehints in any way
   if (Inst->isDebugOrPseudoInst() || Inst->isLifetimeStartOrEnd())
     return 0;
 
@@ -573,7 +575,6 @@ bool IGCRegisterPressurePrinter::runOnFunction(llvm::Function &F) {
   return false;
 }
 
-
 char IGCRegisterPressurePublisher::ID = 0;
 // Register pass to igc-opt
 #define PASS_FLAG3 "igc-pressure-publisher"

IGC/Compiler/tests/RematAddressArithmetic/cloneAddressArithmeticRPEGuess.ll

@@ -0,0 +1,57 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2025 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; REQUIRES: regkeys
+; UNSUPPORTED: system-windows
+; Test that for platforms PVC (and newer) with abort on spill we correctly guess SIMD16 as SIMD size and based on it calculate correct register pressure.
+; For estimate of SIMD32 register pressure wiuld be 16 and rematerialization would be done.
+
+; RUN: igc_opt -platformlnl --typed-pointers %s -S -o - -igc-clone-address-arithmetic --regkey=RematChainLimit=10 --regkey=RematFlowThreshold=100 --regkey=RematRPELimit=10 --dce | FileCheck %s
+
+; CHECK-NOT: remat
+define spir_kernel void @main(double addrspace(1)* %base, i64 %offset, i64 %I, i64 %J) {
+
+  %baseArith = ptrtoint double addrspace(1)* %base to i64
+  %basePtr = mul nuw nsw i64 %offset, 207368
+  %offsetI = mul nsw i64 %I, 1288
+  %offsetJ = shl nsw i64 %J, 3
+
+  %a0 = add i64 %baseArith, 100780848
+  %a1 = add i64 %a0, %basePtr
+  %a2 = add i64 %a1, %offsetI
+  %a3 = add i64 %a2, %offsetJ
+  %a4 = inttoptr i64 %a3 to double addrspace(1)*
+  %r0 = load double, double addrspace(1)* %a4, align 8
+
+  %rr0 = fmul double %r0, 2.0
+
+  store double %rr0, double addrspace(1)* %a4
+  ret void
+}
+
+
+define spir_func void @bar(double addrspace(1)* %base, i64 %offset, i64 %I, i64 %J) {
+  %baseArith = ptrtoint double addrspace(1)* %base to i64
+  %basePtr = mul nuw nsw i64 %offset, 207368
+  %offsetI = mul nsw i64 %I, 1288
+  %offsetJ = shl nsw i64 %J, 3
+
+  %a0 = add i64 %baseArith, 100780848
+  %a1 = add i64 %a0, %basePtr
+  %a2 = add i64 %a1, %offsetI
+  %a3 = add i64 %a2, %offsetJ
+  %a4 = inttoptr i64 %a3 to double addrspace(1)*
+  %a5 = inttoptr i64 %a3 to i64 addrspace(1)*
+  %r0 = load double, double addrspace(1)* %a4, align 8
+
+  %rr0 = fmul double %r0, 2.0
+
+  %cast_a5 = bitcast i64 addrspace(1)* %a5 to double addrspace(1)*
+  store double %rr0, double addrspace(1)* %cast_a5
+  ret void
+}