[Autobackout][FunctionalRegression]Revert of change: 69efb32: Support SPV_INTEL_maximum_registers extension

.

Author: sys-igc

IGC/VectorCompiler/include/vc/Utils/GenX/KernelInfo.h

@@ -26,7 +26,6 @@ SPDX-License-Identifier: MIT
 #include "llvm/GenXIntrinsics/GenXMetadata.h"
 
 #include <cstdint>
-#include <optional>
 #include <type_traits>
 #include <unordered_map>
 
@@ -117,14 +116,6 @@ template <typename Ty = llvm::Value> Ty *getValueAsMetadata(llvm::Metadata *M) {
   return nullptr;
 }
 
-template <typename Ty = llvm::Value>
-Ty *getValueAsMetadata(const llvm::Metadata *M) {
-  if (auto *VM = llvm::dyn_cast<llvm::ValueAsMetadata>(M))
-    if (auto *V = llvm::dyn_cast<Ty>(VM->getValue()))
-      return V;
-  return nullptr;
-}
-
 // Number of barriers can only be 0, 1, 2, 4, 8, 16, 24, 32.
 // Alignment here means choosing nearest overlapping legal number of barriers.
 static unsigned alignBarrierCnt(unsigned BarrierCnt) {
@@ -187,13 +178,6 @@ class KernelMetadata {
     Fixed = 4,
   };
 
-  // TODO: Use SPIR-V headers.
-  enum class ExecutionMode {
-    MaximumRegistersINTEL = 6461,
-    MaximumRegistersIdINTEL = 6462,
-    NamedMaximumRegistersINTEL = 6463
-  };
-
 private:
   const llvm::Function *F = nullptr;
   llvm::MDNode *ExternalNode = nullptr;
@@ -211,9 +195,6 @@ class KernelMetadata {
   std::vector<int> BTIs;
   ArgToImplicitLinearization Linearization;
 
-  // Optional SPIR-V execution mode.
-  std::optional<unsigned> GRFSize;
-
 public:
   // default constructor
   KernelMetadata() {}
@@ -240,8 +221,6 @@ class KernelMetadata {
   void updateBTIndicesMD(std::vector<int> &&BTIs);
   void updateSLMSizeMD(unsigned Size);
 
-  void parseExecutionMode(llvm::MDNode *SpirvExecutionMode);
-
   bool hasArgLinearization(llvm::Argument *Arg) const {
     return Linearization.count(Arg);
   }
@@ -290,8 +269,6 @@ class KernelMetadata {
     return ArgTypeDescs[Idx];
   }
 
-  std::optional<unsigned> getGRFSize() const { return GRFSize; }
-
   enum { AK_NORMAL, AK_SAMPLER, AK_SURFACE };
   RegCategory getArgCategory(unsigned Idx) const {
     switch (getArgKind(Idx) & 7) {

IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

@@ -907,11 +907,10 @@ static bool isExtOperandBaled(Use &U, const GenXBaling *Baling) {
 
 // Args:
 //    HasBarrier - whether kernel has barrier or sbarrier
-static void addKernelAttrsFromMetadata(VISAKernel &Kernel,
-                                       const vc::KernelMetadata &KM,
-                                       const GenXSubtarget *Subtarget,
-                                       const GenXBackendConfig *BC,
-                                       bool HasBarrier) {
+void addKernelAttrsFromMetadata(VISAKernel &Kernel,
+                                const vc::KernelMetadata &KM,
+                                const GenXSubtarget *Subtarget,
+                                bool HasBarrier) {
   unsigned SLMSizeInKb = divideCeil(KM.getSLMSize(), 1024);
   if (SLMSizeInKb > Subtarget->getMaxSlmSize())
     report_fatal_error("SLM size exceeds target limits");
@@ -944,21 +943,6 @@ static void addKernelAttrsFromMetadata(VISAKernel &Kernel,
         static_cast<uint8_t>(KM.getAlignedBarrierCnt(HasBarrier));
     Kernel.AddKernelAttribute("NBarrierCnt", sizeof(BarrierCnt), &BarrierCnt);
   }
-
-  // Default number of registers.
-  unsigned NumGRF = 128;
-  // Set by compile option.
-  if (BC->isAutoLargeGRFMode())
-    NumGRF = 0;
-  if (BC->getGRFSize())
-    NumGRF = BC->getGRFSize();
-  // Set by kernel metadata.
-  if (KM.getGRFSize()) {
-    unsigned NumGRFPerKernel = *KM.getGRFSize();
-    if (NumGRFPerKernel == 0 || Subtarget->isValidGRFSize(NumGRFPerKernel))
-      NumGRF = NumGRFPerKernel;
-  }
-  Kernel.AddKernelAttribute("NumGRF", sizeof(NumGRF), &NumGRF);
 }
 
 // Legalize name for using as filename or in visa asm
@@ -1017,8 +1001,7 @@ void GenXKernelBuilder::runOnKernel() {
   IGC_ASSERT_MESSAGE(Kernel, "Kernel initialization failed!");
   LLVM_DEBUG(dbgs() << "=== PROCESS KERNEL(" << KernelName << ") ===\n");
 
-  addKernelAttrsFromMetadata(*Kernel, TheKernelMetadata, Subtarget,
-                             BackendConfig, HasBarrier);
+  addKernelAttrsFromMetadata(*Kernel, TheKernelMetadata, Subtarget, HasBarrier);
 
   // Set CM target for all functions produced by VC.
   // See visa spec for CMTarget value (section 4, Kernel).
@@ -5835,6 +5818,13 @@ collectFinalizerArgs(StringSaver &Saver, const GenXSubtarget &ST,
   if (ST.needsWANoMaskFusedEU() && !DisableNoMaskWA)
     addArgument("-noMaskWA");
 
+  unsigned GRFSize = BC.getGRFSize();
+  if (GRFSize > 0) {
+    addArgument("-TotalGRFNum");
+    addArgument(to_string(GRFSize));
+  } else if (BC.isAutoLargeGRFMode())
+    addArgument("-autoGRFSelection");
+
   if (ST.hasFusedEU()) {
     addArgument("-fusedCallWA");
     addArgument("1");

IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.cpp

@@ -27,8 +27,6 @@ SPDX-License-Identifier: MIT
 #include "Probe/Assertion.h"
 #include "common/StringMacros.hpp"
 
-#include <unordered_set>
-
 using namespace llvm;
 
 #define DEBUG_TYPE "subtarget"
@@ -276,18 +274,3 @@ bool GenXSubtarget::isInternalIntrinsicSupported(unsigned ID) const {
 
   return true;
 }
-
-bool GenXSubtarget::isValidGRFSize(unsigned Size) const {
-  switch (TargetId) {
-  case GenXSubtarget::XeHP:
-  case GenXSubtarget::XeHPG:
-  case GenXSubtarget::XeLPG:
-  case GenXSubtarget::XeLPGPlus:
-  case GenXSubtarget::XeHPC:
-  case GenXSubtarget::XeHPCVG:
-  case GenXSubtarget::Xe2:
-    return Size == 128 || Size == 256;
-  default:
-    return Size == 128; // platforms <= TGL
-  }
-}

IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h

@@ -457,7 +457,6 @@ class GenXSubtarget final : public GenXGenSubtargetInfo {
   PreDefined_Surface stackSurface() const { return StackSurf; }
 
   bool isIntrinsicSupported(unsigned ID) const;
-  bool isValidGRFSize(unsigned Size) const;
 };
 
 } // namespace llvm

IGC/VectorCompiler/lib/Utils/GenX/KernelInfo.cpp

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2021-2024 Intel Corporation
+Copyright (C) 2021-2022 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -47,12 +47,6 @@ static MDNode *findExternalNode(const Function &F) {
                   genx::KernelMDOp::ArgTypeDescs);
 }
 
-static MDNode *findSpirvExecutionModeNode(const Function &F) {
-  constexpr unsigned FunctionRef = 0;
-  constexpr unsigned MinNumOps = 3;
-  return findNode(F, "spirv.ExecutionMode", FunctionRef, MinNumOps);
-};
-
 void vc::internal::createInternalMD(Function &F) {
   IGC_ASSERT_MESSAGE(!findInternalNode(F),
                      "Internal node has already been created!");
@@ -110,13 +104,6 @@ static RetTy extractConstantIntMD(const MDOperand &Op) {
   return static_cast<RetTy>(V->getZExtValue());
 }
 
-template <typename RetTy = unsigned>
-static RetTy extractConstantIntMD(const Metadata &Op) {
-  const auto *V = getValueAsMetadata<ConstantInt>(&Op);
-  IGC_ASSERT_MESSAGE(V, "Unexpected null value in metadata");
-  return static_cast<RetTy>(V->getZExtValue());
-}
-
 template <typename Cont>
 static void extractConstantsFromMDNode(const MDNode *N, Cont &C) {
   if (!N)
@@ -260,11 +247,6 @@ vc::KernelMetadata::KernelMetadata(const Function *F) {
   }
   if (LinearizationNode)
     Linearization = extractLinearizationMD(*F, LinearizationNode);
-
-  MDNode *SpirvExecutionMode = findSpirvExecutionModeNode(*F);
-  if (!SpirvExecutionMode)
-    return;
-  parseExecutionMode(SpirvExecutionMode);
 }
 
 static MDNode *createArgLinearizationMD(const ImplicitLinearizationInfo &Info) {
@@ -357,32 +339,6 @@ void vc::KernelMetadata::updateSLMSizeMD(unsigned Size) {
                                    ValueAsMetadata::get(C));
 }
 
-void vc::KernelMetadata::parseExecutionMode(MDNode *SpirvExecutionMode) {
-  IGC_ASSERT(SpirvExecutionMode->getNumOperands() >= 3);
-
-  auto &EMode = SpirvExecutionMode->getOperand(1);
-  auto &EModeVal = SpirvExecutionMode->getOperand(2);
-  auto EModeId = static_cast<ExecutionMode>(extractConstantIntMD(EMode));
-  switch (EModeId) {
-  case ExecutionMode::MaximumRegistersINTEL:
-    GRFSize = extractConstantIntMD(*(EModeVal.get()));
-    return;
-  case ExecutionMode::MaximumRegistersIdINTEL: {
-    auto *GRFSizeNode = cast<MDNode>(EModeVal.get());
-    GRFSize = extractConstantIntMD(*(GRFSizeNode->getOperand(0)));
-    return;
-  }
-  case ExecutionMode::NamedMaximumRegistersINTEL: {
-    auto *NamedExecMode = cast<MDString>(EModeVal.get());
-    IGC_ASSERT_EXIT_MESSAGE(!NamedExecMode->getString().compare("AutoINTEL"),
-                            "Unhandled NamedMaximumRegisters value");
-    GRFSize = 0;
-    return;
-  }
-  }
-  IGC_ASSERT_EXIT_MESSAGE(0, "Unhandled execution mode!");
-}
-
 bool vc::hasKernel(const Module &M) {
   NamedMDNode *KernelsMD = M.getNamedMetadata(genx::FunctionMD::GenXKernels);
   if (!KernelsMD)