@@ -13127,10 +13127,10 @@ void EmitPass::emitTypedRead(llvm::Instruction* pInsn)
1312713127 CVariable* flag = nullptr;
1312813128 bool needLoop = ResourceLoopHeader(resource, flag, label);
1312913129 CVariable* tempdst[4] = { nullptr, nullptr, nullptr, nullptr };
13130- bool needsSplit = m_currShader->m_SIMDSize == SIMDMode::SIMD16
13131- && ! m_currShader->m_Platform->supportsSIMD16TypedRW();
13132-
13133- auto instWidth = SIMDMode::SIMD8 ;
13130+ SIMDMode instWidth = std::min(
13131+ m_currShader->m_Platform->supportsSIMD16TypedRW() ? SIMDMode::SIMD16 : SIMDMode::SIMD8,
13132+ m_currShader->m_SIMDSize);
13133+ bool needsSplit = m_currShader->m_SIMDSize > instWidth ;
1313413134
1313513135 if (!needsSplit)
1313613136 {
@@ -13213,9 +13213,10 @@ void EmitPass::emitTypedWrite(llvm::Instruction* pInsn)
1321313213 bool needLoop = ResourceLoopHeader(resource, flag, label);
1321413214 uint parameterLength = 4;
1321513215
13216- bool needsSplit = m_currShader->m_SIMDSize == SIMDMode::SIMD16
13217- && !m_currShader->m_Platform->supportsSIMD16TypedRW();
13218- auto instWidth = SIMDMode::SIMD8;
13216+ SIMDMode instWidth = std::min(
13217+ m_currShader->m_Platform->supportsSIMD16TypedRW() ? SIMDMode::SIMD16 : SIMDMode::SIMD8,
13218+ m_currShader->m_SIMDSize);
13219+ bool needsSplit = m_currShader->m_SIMDSize > instWidth;
1321913220
1322013221 if (!needsSplit)
1322113222 {
@@ -13236,7 +13237,11 @@ void EmitPass::emitTypedWrite(llvm::Instruction* pInsn)
1323613237 }
1323713238 else
1323813239 {
13239- for (uint i = 0; i < 2; ++i)
13240+ IGC_ASSERT(instWidth == SIMDMode::SIMD8 ||
13241+ instWidth == SIMDMode::SIMD16);
13242+ IGC_ASSERT(m_currShader->m_SIMDSize > instWidth);
13243+ const uint numInst = numLanes(m_currShader->m_SIMDSize) / numLanes(instWidth);
13244+ for (uint i = 0; i < numInst; ++i)
1324013245 {
1324113246 CVariable* pPayload = nullptr;
1324213247
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