Init address register to avoid unaligned cross grf access

Zero initialize address register before each usage to avoid
unaligned access that crosses grf boundary.
Some kernels use a mix of indirect accesses with 16 bit,
32 bit and 64 bit alignments. This can create a situation where
inactive channels [of address register] that should be aligned to
32 bits contain data aligned to 16 bits that points to the last
element of a grf register. That situation results in cross grf
boundary access which results in a GPU hang.

(cherry picked from commit ddab4d1)

Author: fda0

IGC/AdaptorOCL/UnifyIROCL.cpp

@@ -211,6 +211,7 @@ static void CommonOCLBasedPasses(OpenCLProgramContext* pContext)
 
     unify_opt_PreProcess(pContext);
     pContext->m_checkFastFlagPerInstructionInCustomUnsafeOptPass = true;
+    pContext->m_mayHaveUnalignedAddressRegister = true;
 
     DumpLLVMIR(pContext, "beforeUnification");
 

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -2775,20 +2775,27 @@ namespace IGC
     void CEncoder::AddrAdd(CVariable* dst, CVariable* src0, CVariable* src1)
     {
         // On ICL+ platforms address register must be initialized if it is used
-        // in VxH indirect addressing to avoid out-of-bounds access on inactive
-        // lanes. VISA initializes address register at the beginning of the
-        // shader which is sufficient for shaders that use address register only
-        // for indirect addressing but is not sufficient if shader also uses
-        // address register in send descriptors. The latter case is handled by
-        // the initialization below.
-        // see VISA Optimizer::resetA0()
+        // in VxH indirect addressing to avoid out-of-bounds on inactive lanes.
+        // VISA initializes address register [see VISA Optimizer::resetA0()]
+        // at the beginning of the shader which is sufficient for some shaders.
+        // It is insufficient if the shader uses:
+        // 1. address register in send descriptors (may cause out of bounds access).
+        // 2. indirect addressing on types with different alignment (may cause cross grf boundary access).
+        // To cover these cases we introduce zero initialization of address register below.
+
         const bool mayUseA0InSendDesc =
             m_program->GetContext()->m_instrTypes.mayHaveIndirectResources;
-        const bool needsA0Reset =
+        const bool mayHaveUnalignedA0 =
+            m_program->GetContext()->m_mayHaveUnalignedAddressRegister;
+
+        const bool softwareNeedsA0Reset =
+            mayUseA0InSendDesc || mayHaveUnalignedA0;
+        const bool platformNeedsA0Reset =
             m_program->m_Platform->NeedResetA0forVxHA0();
+        const bool initializeA0 = (softwareNeedsA0Reset && platformNeedsA0Reset) ||
+            IGC_IS_FLAG_ENABLED(InitializeAddressRegistersBeforeUse);
 
-        if (((mayUseA0InSendDesc && needsA0Reset) ||
-            IGC_IS_FLAG_ENABLED(InitializeAddressRegistersBeforeUse)) &&
+        if (initializeA0 &&
             !dst->IsUniform() &&
             !m_encoderState.m_noMask)
         {

IGC/Compiler/CodeGenPublic.h

@@ -1020,6 +1020,10 @@ namespace IGC
         // Ignore per module fast math flag and use only per instruction fast math flags
         // Add few changes to CustomUnsafeOptPass related to fast flag propagation
         bool m_checkFastFlagPerInstructionInCustomUnsafeOptPass = false;
+        // Specifies if this compilation uses indirect addressing with
+        // differently aligned types. This can result in cross grf boundary
+        // access in inactive channels of address register.
+        bool m_mayHaveUnalignedAddressRegister = false;
         // Map to store global offsets in original global buffer
         std::map<std::string, uint64_t> inlineProgramScopeGlobalOffsets;
         std::vector<std::string> entry_names;

IGC/ocloc_tests/Builtins/intel_sub_group_shuffle.cl

@@ -47,8 +47,10 @@ kernel void test_intel_sub_group_shuffle_non_uniform_non_immediate_index_simd32(
     uint which_sub_group_local_id = ids[gid];
 
 // CHECK: shl (M1, 32) ShuffleTmp(0,0)<1> {{V[0-9]+}}(0,0)<16;8,2> 0x2:uw
+// CHECK-NEXT: mov (M1_NM, 16) A0(0)<1> 0x0:uw
 // CHECK-NEXT: addr_add (M1, 16) A0(0)<1> &[[X:V[0-9]+]] ShuffleTmp(0,0)<1;1,0>
 // CHECK-NEXT: mov (M1, 16) simdShuffle(0,0)<1> r[A0(0),0]<1,0>:d
+// CHECK-NEXT: mov (M5_NM, 16) A0(0)<1> 0x0:uw
 // CHECK-NEXT: addr_add (M5, 16) A0(0)<1> &[[X]] ShuffleTmp(0,16)<1;1,0>
 // CHECK-NEXT: mov (M5, 16) simdShuffle(1,0)<1> r[A0(0),0]<1,0>:d
 
@@ -66,8 +68,10 @@ kernel void test_intel_sub_group_shuffle_non_uniform_non_immediate_index_src_the
     for (uint i = 0; i < num_iterations; ++i)
     {
 // CHECK: shl (M1, 32) ShuffleTmp(0,0)<1> {{V[0-9]+}}(0,0)<16;8,2> 0x2:uw
+// CHECK-NEXT: mov (M1_NM, 16) A0(0)<1> 0x0:uw
 // CHECK-NEXT: addr_add (M1, 16) A0(0)<1> &[[X:V[0-9]+]] ShuffleTmp(0,0)<1;1,0>
 // CHECK-NEXT: mov (M1, 16) first16LanesResult(0,0)<1> r[A0(0),0]<1,0>:d
+// CHECK-NEXT: mov (M5_NM, 16) A0(0)<1> 0x0:uw
 // CHECK-NEXT: addr_add (M5, 16) A0(0)<1> &[[X]] ShuffleTmp(0,16)<1;1,0>
 // CHECK-NEXT: mov (M5, 16) [[X]](1,0)<1> r[A0(0),0]<1,0>:d
 // CHECK-NEXT: mov (M1, 16) [[X]](0,0)<1> first16LanesResult(0,0)<1;1,0>