32-bit hi/lo swap of 64-bit data in vectors fails fix

Adds scalarization for fshl operation

Author: ustachow

IGC/Compiler/Optimizer/Scalarizer.cpp

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2017-2023 Intel Corporation
+Copyright (C) 2017-2024 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -400,9 +400,9 @@ void ScalarizeFunction::dispatchInstructionToScalarize(Instruction* I)
     case Instruction::ShuffleVector:
         scalarizeInstruction(dyn_cast<ShuffleVectorInst>(I));
         break;
-        //case Instruction::Call :
-        //  scalarizeInstruction(dyn_cast<CallInst>(I));
-        //  break;
+    case Instruction::Call :
+        scalarizeInstruction(dyn_cast<CallInst>(I));
+        break;
     case Instruction::Alloca:
         scalarizeInstruction(dyn_cast<AllocaInst>(I));
         break;
@@ -1024,7 +1024,52 @@ void ScalarizeFunction::scalarizeInstruction(CallInst* CI)
     V_PRINT(scalarizer, "\t\tCall instruction\n");
     IGC_ASSERT_MESSAGE(CI, "instruction type dynamic cast failed");
 
-    recoverNonScalarizableInst(CI);
+    Function* CalledFunc = CI->getCalledFunction();
+    if (CalledFunc && CalledFunc->getName().startswith("llvm.fshl"))
+    {
+        V_PRINT(scalarizer, "\t\tScalarizing fshl intrinsic\n");
+
+        IGCLLVM::FixedVectorType* instType = dyn_cast<IGCLLVM::FixedVectorType>(CI->getType());
+        if (!instType) {
+            recoverNonScalarizableInst(CI);
+            return;
+        }
+
+        SCMEntry* newEntry = getSCMEntry(CI);
+
+        unsigned numElements = int_cast<unsigned>(instType->getNumElements());
+
+        SmallVector<Value*, MAX_INPUT_VECTOR_WIDTH> operand0;
+        SmallVector<Value*, MAX_INPUT_VECTOR_WIDTH> operand1;
+        SmallVector<Value*, MAX_INPUT_VECTOR_WIDTH> operand2;
+        bool op0IsConst, op1IsConst, op2IsConst;
+
+        obtainScalarizedValues(operand0, &op0IsConst, CI->getOperand(0), CI);
+        obtainScalarizedValues(operand1, &op1IsConst, CI->getOperand(1), CI);
+        obtainScalarizedValues(operand2, &op2IsConst, CI->getOperand(2), CI);
+
+        SmallVector<Value*, MAX_INPUT_VECTOR_WIDTH> newScalarizedInsts;
+        newScalarizedInsts.resize(numElements);
+        for (unsigned i = 0; i < numElements; i++)
+        {
+            Type* scalarType = operand0[i]->getType();
+            Value* scalarFshl = CallInst::Create(
+                Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fshl, { scalarType }),
+                { operand0[i], operand1[i], operand2[i] },
+                CI->getName() + ".scalar",
+                CI
+            );
+            newScalarizedInsts[i] = scalarFshl;
+        }
+
+        updateSCMEntryWithValues(newEntry, &(newScalarizedInsts[0]), CI, true);
+
+        m_removedInsts.insert(CI);
+    }
+    else
+    {
+        recoverNonScalarizableInst(CI);
+    }
 }
 
 void ScalarizeFunction::scalarizeInstruction(AllocaInst* AI)

IGC/Compiler/tests/ScalarizeFunction/fshl_vectors.ll

@@ -0,0 +1,33 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+;
+; RUN: igc_opt --igc-scalarize -S < %s | FileCheck %s
+; ------------------------------------------------
+; ScalarizeFunction
+; ------------------------------------------------
+
+declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
+declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
+
+define spir_kernel void @test_basic_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) {
+; CHECK-LABEL: @test_basic_v4i64(
+; CHECK: call i64 @llvm.fshl.i64(i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}})
+; CHECK: call i64 @llvm.fshl.i64(i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}})
+; CHECK: call i64 @llvm.fshl.i64(i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}})
+; CHECK: call i64 @llvm.fshl.i64(i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}})
+  %res = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c)
+  ret void
+}
+
+define spir_kernel void @test_basic_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; CHECK-LABEL: @test_basic_v2i32(
+; CHECK: call i32 @llvm.fshl.i32(i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}})
+; CHECK: call i32 @llvm.fshl.i32(i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}})
+  %res = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)
+  ret void
+}