Skip to content

Commit 71d7269

Browse files
esukhovigcbot
esukhov
authored and
igcbot
committed
IGCVectorizer do not process <1 x float>
Additional check that fixes the bug with <1 x float> dpases.
1 parent e5660e3 commit 71d7269

File tree

3 files changed

+74
-13
lines changed

3 files changed

+74
-13
lines changed

‎IGC/Compiler/CISACodeGen/IGCVectorizer.cpp‎

Lines changed: 28 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -87,39 +87,38 @@ IGC_INITIALIZE_PASS_BEGIN(IGCVectorizer, PASS_FLAG2, PASS_DESCRIPTION2, PASS_CFG
8787
IGC_INITIALIZE_PASS_DEPENDENCY(CodeGenContextWrapper)
8888
IGC_INITIALIZE_PASS_END(IGCVectorizer, PASS_FLAG2, PASS_DESCRIPTION2, PASS_CFG_ONLY2, PASS_ANALYSIS2)
8989

90-
#define OutputLogStreamM OutputLogStream
9190
#define DEBUG IGC_IS_FLAG_ENABLED(VectorizerLog)
9291
#define PRINT_LOG(Str) \
9392
if (DEBUG) { \
94-
OutputLogStreamM << Str; \
93+
OutputLogStream << Str; \
9594
writeLog(); \
9695
}
9796
#define PRINT_LOG_NL(Str) \
9897
if (DEBUG) { \
99-
OutputLogStreamM << Str << "\n"; \
98+
OutputLogStream << Str << "\n"; \
10099
writeLog(); \
101100
}
102101
#define PRINT_INST(I) \
103102
if (DEBUG) { \
104-
I->print(OutputLogStreamM, false); \
103+
I->print(OutputLogStream, false); \
105104
}
106105
#define PRINT_INST_NL(I) \
107106
if (DEBUG) { \
108107
if (I) { \
109-
I->print(OutputLogStreamM, false); \
108+
I->print(OutputLogStream, false); \
110109
} else { \
111110
PRINT_LOG("NULL"); \
112111
} \
113-
OutputLogStreamM << "\n"; \
112+
OutputLogStream << "\n"; \
114113
}
115114
#define PRINT_DECL_NL(I) \
116115
if (DEBUG) { \
117116
if (I) { \
118-
I->print(OutputLogStreamM); \
117+
I->print(OutputLogStream); \
119118
} else { \
120119
PRINT_LOG("NULL"); \
121120
} \
122-
OutputLogStreamM << "\n"; \
121+
OutputLogStream << "\n"; \
123122
}
124123
#define PRINT_DS(Str, DS) \
125124
if (DEBUG) { \
@@ -136,9 +135,13 @@ IGC_INITIALIZE_PASS_END(IGCVectorizer, PASS_FLAG2, PASS_DESCRIPTION2, PASS_CFG_O
136135
IGCVectorizer::IGCVectorizer() : FunctionPass(ID) { initializeIGCVectorizerPass(*PassRegistry::getPassRegistry()); };
137136

138137
void IGCVectorizer::writeLog() {
139-
if (IGC_IS_FLAG_ENABLED(VectorizerLog) && OutputLogFile->is_open())
138+
139+
if (IGC_IS_FLAG_ENABLED(VectorizerLog) && IGC_IS_FLAG_DISABLED(VectorizerLogToErr) && OutputLogFile->is_open())
140140
*OutputLogFile << OutputLogStream.str();
141141

142+
if (IGC_IS_FLAG_ENABLED(VectorizerLog) && IGC_IS_FLAG_ENABLED(VectorizerLogToErr))
143+
llvm::errs() << OutputLogStream.str();
144+
142145
OutputLogStream.str().clear();
143146
}
144147

@@ -184,11 +187,12 @@ void IGCVectorizer::findInsertElementsInDataFlow(llvm::Instruction *I, VecArr &C
184187
bool IsConstant = llvm::isa<llvm::Constant>(Op);
185188
bool IsExplored = Explored.count(Op);
186189
bool IsInsertElement = llvm::isa<InsertElementInst>(Op);
190+
bool IsVectorTyped = Op->getType()->isVectorTy();
187191

188192
if (IsInsertElement)
189193
Chain.push_back(Op);
190194

191-
bool Skip = IsConstant || IsExplored || IsInsertElement;
195+
bool Skip = IsConstant || IsExplored || IsInsertElement || !IsVectorTyped;
192196
if (Skip)
193197
continue;
194198

@@ -275,14 +279,17 @@ bool isIntrinsicSafe(Instruction *I) {
275279

276280
bool isSafeToVectorize(Instruction *I) {
277281

282+
bool IsInsertOrExtract = llvm::isa<ExtractElementInst>(I) || llvm::isa<InsertElementInst>(I);
283+
// the only typed instructions we add to slices => Insert or Extract elements
284+
bool IsVectorTyped = I->getType()->isVectorTy() && !IsInsertOrExtract;
278285
bool isFloat = isFloatTyped(I);
279286

280287
// this is a very limited approach for vectorizing but it's safe
281-
bool Result = isPHISafe(I) || llvm::isa<ExtractElementInst>(I) || llvm::isa<InsertElementInst>(I) ||
288+
bool Result = isPHISafe(I) || IsInsertOrExtract ||
282289
(llvm::isa<FPTruncInst>(I) && IGC_GET_FLAG_VALUE(VectorizerAllowFPTRUNC)) || isBinarySafe(I) ||
283290
isIntrinsicSafe(I);
284291

285-
return Result && isFloat;
292+
return Result && isFloat && !IsVectorTyped;
286293
}
287294

288295
bool IGCVectorizer::handlePHI(VecArr &Slice) {
@@ -414,10 +421,13 @@ InsertElementInst *IGCVectorizer::createVector(VecArr &Slice, Instruction *Inser
414421
PRINT_LOG_NL("insertPoint moved to FirstNonPHI");
415422
}
416423

424+
InsertElementInst *CreatedInsert = nullptr;
417425
llvm::Type *elementType = Slice[0]->getType();
426+
if (elementType->isVectorTy())
427+
return CreatedInsert;
428+
418429
llvm::VectorType *vectorType = llvm::FixedVectorType::get(elementType, Slice.size());
419430
llvm::Value *UndefVector = llvm::UndefValue::get(vectorType);
420-
InsertElementInst *CreatedInsert = nullptr;
421431

422432
for (size_t i = 0; i < Slice.size(); i++) {
423433
llvm::Value *index = llvm::ConstantInt::get(llvm::Type::getInt32Ty(M->getContext()), i);
@@ -1076,6 +1086,11 @@ bool IGCVectorizer::runOnFunction(llvm::Function &F) {
10761086
InSt.Final = elFinal;
10771087
clusterInsertElement(InSt);
10781088

1089+
if (getVectorSize(InSt.Final) == 1) {
1090+
PRINT_LOG_NL("degenerate insert of the type <1 x float> -> rejected");
1091+
continue;
1092+
}
1093+
10791094
if (InSt.Vec.size() != getVectorSize(InSt.Final)) {
10801095
PRINT_LOG_NL("partial insert -> rejected");
10811096
continue;

‎IGC/Compiler/tests/IGCVectorizer/vectorizer-1xfloat-degenerate-case.ll‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
; REQUIRES: regkeys
2+
; RUN: igc_opt --igc-vectorizer -S -dce --regkey=VectorizerLog=1 --regkey=VectorizerLogToErr=1 < %s 2>&1 | FileCheck %s
3+
4+
; CHECK: degenerate insert of the type <1 x float> -> rejected
5+
; CHECK: degenerate insert of the type <1 x float> -> rejected
6+
7+
; Function Attrs: convergent nounwind
8+
define spir_kernel void @widget() #0 {
9+
bb:
10+
br label %bb1
11+
12+
bb1: ; preds = %bb1, %bb
13+
%tmp = phi float [ 1.000000e+00, %bb ], [ 0.000000e+00, %bb1 ]
14+
%tmp2 = phi float [ 0.000000e+00, %bb ], [ %tmp18, %bb1 ]
15+
%tmp3 = phi float [ 0.000000e+00, %bb ], [ %tmp20, %bb1 ]
16+
%tmp5 = call float @llvm.exp2.f32(float %tmp)
17+
%tmp6 = fmul contract float %tmp2, %tmp5
18+
%tmp7 = fmul contract float %tmp3, %tmp5
19+
%tmp9 = insertelement <1 x float> zeroinitializer, float %tmp6, i64 0
20+
%tmp10 = insertelement <1 x float> zeroinitializer, float %tmp7, i64 0
21+
%tmp11 = call <1 x float> @llvm.genx.GenISA.sub.group.dpas.v1f32.v1f32.v1i16.v8i32(<1 x float> %tmp9, <1 x i16> zeroinitializer, <8 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0, i1 false)
22+
%tmp12 = call <1 x float> @llvm.genx.GenISA.sub.group.dpas.v1f32.v1f32.v1i16.v8i32(<1 x float> %tmp10, <1 x i16> zeroinitializer, <8 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0, i1 false)
23+
%tmp18 = extractelement <1 x float> %tmp11, i64 0
24+
%tmp20 = extractelement <1 x float> %tmp12, i64 0
25+
br label %bb1
26+
}
27+
28+
; Function Attrs: convergent nounwind readnone willreturn
29+
declare <1 x float> @llvm.genx.GenISA.sub.group.dpas.v1f32.v1f32.v1i16.v8i32(<1 x float>, <1 x i16>, <8 x i32>, i32, i32, i32, i32, i1) #1
30+
31+
; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
32+
declare float @llvm.exp2.f32(float) #2
33+
34+
; uselistorder directives
35+
uselistorder <1 x float> (<1 x float>, <1 x i16>, <8 x i32>, i32, i32, i32, i32, i1)* @llvm.genx.GenISA.sub.group.dpas.v1f32.v1f32.v1i16.v8i32, { 1, 0 }
36+
37+
attributes #0 = { convergent nounwind }
38+
attributes #1 = { convergent nounwind readnone willreturn }
39+
attributes #2 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
40+
41+
!igc.functions = !{!0}
42+
43+
!0 = distinct !{void ()* @widget, !1}
44+
!1 = distinct !{!2}
45+
!2 = distinct !{!"sub_group_size", i32 16}

‎IGC/common/igc_flags.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1536,6 +1536,7 @@ DECLARE_IGC_REGKEY(bool, DumpRegPressureEstimate, false, "Dump RegPressureEstima
15361536
DECLARE_IGC_REGKEY(debugString, DumpRegPressureEstimateFilter, 0,
15371537
"Only dump RegPressureEstimate for functions matching the given regex", false)
15381538
DECLARE_IGC_REGKEY(bool, VectorizerLog, false, "Dump Vectorizer Log, usefull for analyzing vectorization issues", true)
1539+
DECLARE_IGC_REGKEY(bool, VectorizerLogToErr, false, "Dump Vectorizer Log to stdErr", true)
15391540
DECLARE_IGC_REGKEY(bool, EnableReusingXYZWStoreConstPayload, true, "Enable reusing XYZW stores const payload", false)
15401541
DECLARE_IGC_REGKEY(bool, EnableReusingLSCStoreConstPayload, false, "Enable reusing LSC stores const payload", false)
15411542
DECLARE_IGC_REGKEY(bool, AllowSIMD16DropForXE2, true, "Controls the switch for XE2 simd16 drop", false)

0 commit comments

Comments
 (0)