Refactor some 2d block read

For some of 2D block read whose block size is half a GRF, the special
handling (replacing it with the equivalent single-block read) is moved
from emitVISAPass to LSCFuncsResolution so that address payload version
can handle it correctly as well.

There should be no functional change.

Author: jgu222

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -24745,25 +24745,6 @@ void EmitPass::emitLSC2DBlockOperation(llvm::GenIntrinsicInst* inst)
         destination = BroadcastIfUniform(GetSymbol(inst->getOperand(storeDestinationOperandId)));
     }
 
-    // Special handling of the following:
-    //    intel_sub_group_2d_block_read_8b_1r32x2c
-    //    intel_sub_group_2d_block_read_16b_1r16x2c
-    //    intel_sub_group_2d_block_read_32b_1r8x2c
-    // They are defined to return 64 bytes, but the HW block read returns 128 bytes (two GRFs,
-    // as a block size must be multiple of GRF, unused part is zero-padded). Additional mov
-    // instructions are needed to pack the lower halves of each GRF as the final return value.
-    //
-    // Here, using equivalent single-block read to avoid those mov instructions by
-    // just doubling their width.
-    if (isRead && !isPrefetch && !isTranspose && !isVnni &&
-        numBlocksV == 2 && blockHeight == 1 &&
-        (elemSizeInBits * blockWidth) == 256 &&
-        m_currShader->m_Platform->getGRFSize() == 64)
-    {
-        blockWidth = (2 * blockWidth);
-        numBlocksV = 1;
-    }
-
     bool emu_read = (isRead && isTranspose &&
         (elemSizeInBits == 8 || elemSizeInBits == 16));
     if (!emu_read) {

IGC/Compiler/Optimizer/OpenCLPasses/LSCFuncs/LSCFuncsResolution.cpp

@@ -950,6 +950,29 @@ Instruction* LSCFuncsResolution::CreateSubGroup2DBlockOperation(llvm::CallInst&
         {
             IGC_ASSERT_MESSAGE(funcName.consume_front("v2"), "Unrecognized v element in __builtin_IB_subgroup_block_read/write.");
         }
+
+        // Special handling of the following when GRF size = 64 bytes
+        //    intel_sub_group_2d_block_read_8b_1r32x2c  (u8_m1k32v2)
+        //    intel_sub_group_2d_block_read_16b_1r16x2c (u16_m1k16v2)
+        //    intel_sub_group_2d_block_read_32b_1r8x2c  (u32_m1k8v2)
+        // They are defined to return 64 bytes, but the HW block read
+        // returns 128 bytes (two GRFs, as a block size must be multiple
+        // of GRF, unused part is zero-padded. Note that those APIs have
+        // their block size to be multiple of GRF (1 GRF) when GRF size
+        // is 32 bytes). Additional mov instructions are needed to pack
+        // the lower halves of each GRF as the final return value.
+        //
+        // For those cases, instead of 2 blocks, using equivalent single-block
+        // read to avoid those mov instructions by just doubling their width:
+        //   u8_m1k32v2  --> u8_m1k64v1
+        //   u16_m1k16v2 --> u16_m1k32v1
+        //   u32_m1k8v2  --> u32_m1k16v1
+        if (m_pCtx->platform.getGRFSize() == 64 && isRead && !isPrefetch &&
+            numBlocksV == 2 && tileHeight == 1 && (elemSize * tileWidth) == 256)
+        {
+            numBlocksV = 1;
+            tileWidth *= 2;
+        }
     }
     else if (isTranspose && !isVnniTransform)
     {