Indirect regions legalization improvement

Change-Id: Id2a58b95279a8bb1558583e594330d278815ec4c

Author: azabazno

IGC/VectorCompiler/lib/GenXCodeGen/GenXAlignmentInfo.cpp

@@ -37,6 +37,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 //===----------------------------------------------------------------------===//
 #define DEBUG_TYPE "GENX_ALIGNMENT_INFO"
 
+#include "IGC/common/StringMacros.hpp"
+
 #include <algorithm>
 #include "GenX.h"
 #include "GenXAlignmentInfo.h"
@@ -63,6 +65,7 @@ Alignment AlignmentInfo::get(Value *V)
   if (auto C = dyn_cast<Constant>(V))
     return Alignment(C);
   auto Inst = dyn_cast<Instruction>(V);
+
   if (!Inst) {
     // An Argument has unknown alignment.
     // (FIXME: We may need to do better than this, tracing the value of the
@@ -141,8 +144,10 @@ Alignment AlignmentInfo::get(Value *V)
     Alignment A(0, 0); // assume unknown
     if (BinaryOperator *BO = dyn_cast<BinaryOperator>(WorkInst)) {
       A = Alignment(); // assume uncomputed
-      Alignment A0 = getFromInstMap(BO->getOperand(0));
-      Alignment A1 = getFromInstMap(BO->getOperand(1));
+      auto *Op0 = BO->getOperand(0);
+      auto *Op1 = BO->getOperand(1);
+      Alignment A0 = getFromInstMap(Op0);
+      Alignment A1 = getFromInstMap(Op1);
       if (!A0.isUncomputed() && !A1.isUncomputed()) {
         switch (BO->getOpcode()) {
           case Instruction::Add:
@@ -164,9 +169,17 @@ Alignment AlignmentInfo::get(Value *V)
             } else
               A = Alignment::getUnknown();
             break;
-        default:
-          A = Alignment::getUnknown();
-          break;
+          case Instruction::And:
+            if (auto *CI0 = dyn_cast<ConstantInt>(Op0)) {
+              A = A1.logicalAnd(CI0);
+            } else if (auto *CI1 = dyn_cast<ConstantInt>(Op1)) {
+              A = A0.logicalAnd(CI1);
+            } else
+              A = Alignment::getUnknown();
+            break;
+          default:
+            A = Alignment::getUnknown();
+            break;
         }
       }
     } else if (CastInst *CI = dyn_cast<CastInst>(WorkInst)) {
@@ -201,11 +214,11 @@ Alignment AlignmentInfo::get(Value *V)
       switch (GenXIntrinsic::getGenXIntrinsicID(WorkInst)) {
         case GenXIntrinsic::genx_rdregioni:
         case GenXIntrinsic::genx_rdregionf: {
-          // Handle the case of reading a scalar from element 0 of a vector, as
+          // Handle the case of reading a scalar from element of a vector, as
           // a trunc from i32 to i16 is lowered to a bitcast to v2i16 then a
           // rdregion.
           Region R(WorkInst, BaleInfo());
-          if (!R.Indirect && !R.Offset)
+          if (!R.Indirect && (R.NumElements == 1))
             A = getFromInstMap(WorkInst->getOperand(0));
           else
             A = Alignment(0, 0);
@@ -275,7 +288,30 @@ Alignment::Alignment(unsigned C)
 {
   LogAlign = countTrailingZeros(C);
   ExtraBits = 0;
-  ConstBits = (C < 0x7fffffff)? C : 0x7fffffff;
+  ConstBits = (C < MaskForUnknown) ? C : MaskForUnknown;
+}
+
+Alignment Alignment::getAlignmentForConstant(Constant *C) {
+  IGC_ASSERT(!isa<VectorType>(C->getType()));
+  Alignment A;
+  A.setUncomputed();
+  if (isa<UndefValue>(C)) {
+    A.LogAlign = 31;
+    A.ExtraBits = 0;
+    A.ConstBits = MaskForUnknown;
+  } else if (auto CI = dyn_cast<ConstantInt>(C)) {
+    int64_t SVal = CI->getSExtValue();
+    // Get least significant bits to count LogAlign
+    unsigned LSBBits = SVal & UnsignedAllOnes;
+    A.LogAlign = countTrailingZeros(LSBBits);
+
+    A.ExtraBits = 0;
+    A.ConstBits = MaskForUnknown;
+    if (SVal < MaskForUnknown && SVal >= 0 &&
+        SVal <= std::numeric_limits<unsigned>::max())
+      A.ConstBits = static_cast<unsigned>(SVal);
+  }
+  return A;
 }
 
 /***********************************************************************
@@ -284,19 +320,18 @@ Alignment::Alignment(unsigned C)
 Alignment::Alignment(Constant *C)
 {
   setUncomputed();
-  if (isa<VectorType>(C->getType()))
-    C = C->getAggregateElement(0U);
-  if (isa<UndefValue>(C)) {
-    LogAlign = 31;
-    ExtraBits = 0;
-    ConstBits = 0x7fffffff;
-  } else if (auto CI = dyn_cast<ConstantInt>(C)) {
-    LogAlign = countTrailingZeros((unsigned)(CI->getSExtValue()));
-    ExtraBits = 0;
-    ConstBits = 0x7fffffff;
-    if (CI->getSExtValue() < 0x7fffffff && CI->getSExtValue() >= 0)
-      ConstBits = (unsigned)(CI->getSExtValue());
+  if (auto *VT = dyn_cast<VectorType>(C->getType())) {
+    // Take splat if exists
+    if (auto *SplatVal = C->getSplatValue())
+      C = SplatVal;
+    else {
+      // Otherwise be conservative and pretend alignment
+      // unknown for non-splat vectors
+      *this = Alignment::getUnknown();
+      return;
+    }
   }
+  *this = getAlignmentForConstant(C);
 }
 
 /***********************************************************************
@@ -365,6 +400,24 @@ Alignment Alignment::mul(Alignment Other) const
   return Alignment(MinLogAlign, ExtraBits2 & ((1 << MinLogAlign) - 1));
 }
 
+/***********************************************************************
+ * logicalAnd : logical and two alignments. Only constant int supported.
+ */
+Alignment Alignment::logicalAnd(ConstantInt *CI) const {
+  IGC_ASSERT(!isUncomputed() && CI);
+  // If value doesn't fit into unsigned then be conservative and pretend
+  // that alignement is unknown
+  int64_t Val = CI->getSExtValue();
+  if (Val < std::numeric_limits<int>::min() ||
+      Val > std::numeric_limits<int>::max())
+    return Alignment::getUnknown();
+  unsigned UVal = static_cast<unsigned>(std::abs(Val));
+  unsigned ValLSB = countTrailingZeros(UVal, ZB_Width);
+  // Chop off constant bits according to maximum log align
+  unsigned NewLogAlign = std::max(ValLSB, LogAlign);
+  return Alignment(NewLogAlign, UVal & ((1 << NewLogAlign) - 1));
+}
+
 /***********************************************************************
  * getFromInstMap : get the alignment of a value, direct from InstMap if
  * found else return Unknown, Alignment(0, 0)

IGC/VectorCompiler/lib/GenXCodeGen/GenXAlignmentInfo.h

@@ -71,12 +71,16 @@ class Alignment {
   unsigned LogAlign;
   unsigned ExtraBits;
   unsigned ConstBits;
+
+  static constexpr unsigned MaskForUnknown = 0x7fffffff;
+  static constexpr unsigned UnsignedAllOnes = 0xffffffff;
+
 public:
   // No-arg constructor sets to uncomputed state.
   Alignment() { setUncomputed(); }
   // Constructor given LogAlign and ExtraBits fields.
   Alignment(unsigned LogAlign, unsigned ExtraBits)
-  : LogAlign(LogAlign), ExtraBits(ExtraBits), ConstBits(0x7fffffff) {}
+      : LogAlign(LogAlign), ExtraBits(ExtraBits), ConstBits(MaskForUnknown) {}
   // Constructor given literal value.
   Alignment(unsigned C);
   // Constructor given Constant.
@@ -103,11 +107,17 @@ class Alignment {
   Alignment add(Alignment Other) const;
   // Mul one Alignment with another Alignment
   Alignment mul(Alignment Other) const;
+  // Logical and Alignment with constant integer
+  Alignment logicalAnd(ConstantInt *CI) const;
 
   // accessors
-  bool isUncomputed() const { return LogAlign == 0xffffffff; }
-  bool isUnknown() const { return LogAlign == 0 && ConstBits == 0x7fffffff; }
-  bool isConstant() const { return !isUncomputed() && ConstBits != 0x7fffffff; }
+  bool isUncomputed() const { return LogAlign == UnsignedAllOnes; }
+  bool isUnknown() const {
+    return LogAlign == 0 && ConstBits == MaskForUnknown;
+  }
+  bool isConstant() const {
+    return !isUncomputed() && ConstBits != MaskForUnknown;
+  }
   unsigned getLogAlign() const { IGC_ASSERT(!isUncomputed()); return LogAlign; }
   unsigned getExtraBits() const { IGC_ASSERT(!isUncomputed()); return ExtraBits; }
   int64_t getConstBits() const { IGC_ASSERT(isConstant()); return ConstBits; }
@@ -117,14 +127,15 @@ class Alignment {
             ExtraBits == Rhs.ExtraBits &&
             ConstBits == Rhs.ConstBits);
   }
+  static Alignment getAlignmentForConstant(Constant *C);
   // Debug dump/print
   void dump() const;
   void print(raw_ostream &OS) const;
 private:
   void setUncomputed() {
-    LogAlign = 0xffffffff;
+    LogAlign = UnsignedAllOnes;
     ExtraBits = 0;
-    ConstBits = 0x7fffffff;
+    ConstBits = MaskForUnknown;
   }
 };
 

IGC/VectorCompiler/lib/GenXCodeGen/GenXRegion.cpp

@@ -361,13 +361,8 @@ unsigned Region::getLegalSize(unsigned Idx, bool Allow2D,
         // operand or is a 1D source operand (so GenXCisaBuilder can turn it
         // into Nx1 instead of 1xN).  We use Allow2D as a proxy for "is source
         // operand".
-        unsigned GRFsPerIndirect = 1;
-        IGC_ASSERT(ST);
-        if (ST->hasIndirectGRFCrossing() &&
-          // SKL+. See if we can allow GRF crossing.
-            (Allow2D || !is2D())) {
-            GRFsPerIndirect = 2;
-        }
+        unsigned GRFsPerIndirect =
+            genx::getNumGRFsPerIndirectForRegion(*this, ST, Allow2D);
         unsigned Last = (NumElements / Width - 1) * VStride + (Width - 1) * Stride;
         unsigned Max = InputNumElements - Last - 1 + RealIdx;
         unsigned Min = RealIdx;
@@ -378,11 +373,11 @@ unsigned Region::getLegalSize(unsigned Idx, bool Allow2D,
         else if (MinMaxGRFDiff == 1 && GRFsPerIndirect > 1)
           ElementsToBoundary = ElementsPerGRF - (Max & (ElementsPerGRF - 1));
         // We may be able to refine an indirect region legal width further...
-        if (exactLog2(ParentWidth) >= 0
-            && ParentWidth <= ElementsPerGRF) {
-          // ParentWidth tells us that a row of our region cannot cross a GRF
-          // boundary. Say that the boundary is at the next multiple of
-          // ParentWidth.
+        if (exactLog2(ParentWidth) >= 0 &&
+            ParentWidth <= GRFsPerIndirect * ElementsPerGRF) {
+          // ParentWidth tells us that a row of our region cannot cross a
+          // possible number of elements addressed by indirect region. Say that
+          // the boundary is at the next multiple of ParentWidth.
           ElementsToBoundary = std::max(ParentWidth - RealIdx % ParentWidth,
                 ElementsToBoundary);
         } else if (!isa<VectorType>(Indirect->getType())) {

IGC/VectorCompiler/lib/GenXCodeGen/GenXRegionCollapsing.cpp

@@ -113,6 +113,7 @@ class GenXRegionCollapsing : public FunctionPass {
   Value *insertOp(Instruction::BinaryOps Opcode, Value *Lhs, Value *Rhs,
                   const Twine &Name, Instruction *InsertBefore,
                   const DebugLoc &DL);
+  bool isSingleElementRdRExtract(Instruction *I);
 };
 
 }// end namespace llvm
@@ -579,6 +580,21 @@ void GenXRegionCollapsing::processRdRegion(Instruction *InnerRd)
       LLVM_DEBUG(dbgs() << "Cannot normalize element type\n");
       return;
     }
+
+    // If it's a signle element extract from an indirect region
+    // then check if there exist some other extracts
+    if (OuterR.Indirect && (OuterR.NumElements != 1) &&
+        isSingleElementRdRExtract(InnerRd)) {
+      auto NumExtracts = llvm::count_if(OuterRd->uses(), [this](Use &U) {
+        return isSingleElementRdRExtract(cast<Instruction>(U.getUser()));
+      });
+      // If there are some more extracts except this one (InnerRd)
+      // then not combine these regions to prevent generation
+      // of extra address conversions for a combined region
+      if (NumExtracts > 1)
+        return;
+    }
+
     Region CombinedR;
     if (!combineRegions(&OuterR, &InnerR, &CombinedR))
       return; // cannot combine
@@ -1463,3 +1479,9 @@ Value *GenXRegionCollapsing::insertOp(Instruction::BinaryOps Opcode, Value *Lhs,
   return Inst;
 }
 
+bool GenXRegionCollapsing::isSingleElementRdRExtract(Instruction *I) {
+  if (!GenXIntrinsic::isRdRegion(I))
+    return false;
+  Region R = Region::getWithOffset(I, /*WantParentWidth=*/true);
+  return R.NumElements == 1 && !R.Indirect;
+}

IGC/VectorCompiler/lib/GenXCodeGen/GenXUtil.cpp

@@ -49,6 +49,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "llvm/IR/Metadata.h"
 #include "llvm/IR/Module.h"
 
+#include "llvmWrapper/IR/InstrTypes.h"
+
 #include "Probe/Assertion.h"
 #include <iterator>
 
@@ -1805,3 +1807,16 @@ bool genx::breakConstantExprs(Function *F) {
   }
   return Modified;
 }
+
+unsigned genx::getNumGRFsPerIndirectForRegion(const genx::Region &R,
+                                              const GenXSubtarget *ST,
+                                              bool Allow2D) {
+  IGC_ASSERT(R.Indirect && "Indirect region expected");
+  IGC_ASSERT(ST);
+  if (ST->hasIndirectGRFCrossing() &&
+      // SKL+. See if we can allow GRF crossing.
+      (Allow2D || !R.is2D())) {
+    return 2;
+  }
+  return 1;
+}

IGC/VectorCompiler/lib/GenXCodeGen/GenXUtil.h

@@ -524,6 +524,9 @@ bool breakConstantExprs(Instruction *I);
 // breakConstantExprs : break constant expressions in function F.
 // Return true if any modifications have been made, false otherwise.
 bool breakConstantExprs(Function *F);
+// Get possible number of GRFs for indirect region
+unsigned getNumGRFsPerIndirectForRegion(const genx::Region &R,
+                                        const GenXSubtarget *ST, bool Allow2D);
 
 // BinaryDataAccumulator: it's a helper class to accumulate binary data
 // in one buffer.