[Autobackout][FuncReg]Revert of change: 1f305a2

Try to replace isInSimdFlow() with isDivergent() by using a new
function isAllLaneActive().

isInSimdFlow() has semantics meaning that all lanes (32) are
active if isInSimdFlow() is false, that is, !isInSimdFlow() == NoMask.
This is not equavalent to isDivergent(). Thus isAllLaneActive() is
added to mimic !isInSimdFlow().

This change should have no effect on igc.  It is not expected to affect
CM either.

Change-Id: Iad39a4e03cf97976bde9421fad158532999cc93e

Author: jgu222

visa/FlowGraph.cpp

@@ -5887,17 +5887,6 @@ void G4_BB::resetLocalId()
     }
 }
 
-bool G4_BB::isAllLaneActive() const
-{
-    G4_Kernel* pK = parent->getKernel();
-    if (pK->getIntKernelAttribute(Attributes::ATTR_Target) == VISA_CM && !isDivergent())
-    {
-        // CM: if BB isn't divergent, all lanes (32) must be active (dmask = 0xFFFFFFFF)
-        return true;
-    }
-    return false;
-}
-
 const char* G4_BB::getBBTypeStr() const
 {
     switch (getBBType()) {

visa/FlowGraph.h

@@ -426,7 +426,6 @@ class G4_BB
     bool     isInSimdFlow() const             {return inSimdFlow;}
     void     setDivergent(bool val) { divergent = val; }
     bool     isDivergent() const    { return divergent; }
-    bool     isAllLaneActive() const;
     unsigned getScopeID() { return scopeID; }
     void setScopeID(unsigned id) { scopeID = id; }
 

visa/HWConformity.cpp

@@ -399,7 +399,7 @@ G4_Operand* HWConformity::insertMovBefore(
     // due to old BDW regioning rule we need NoMask inst here so they can be split
     if (builder.getOptions()->isTargetCM() && builder.getPlatform() == GENX_BDW)
     {
-        if (!bb->isAllLaneActive())
+        if (bb->isInSimdFlow())
         {
             newInstEMask = InstOpt_WriteEnable;
         }
@@ -1530,7 +1530,7 @@ bool HWConformity::fixDstAlignment( INST_LIST_ITER i, G4_BB* bb, G4_Type extype,
 
     // optimize initialization instructions
     if( inst->opcode() == G4_mov && src0->isImm() &&
-        ( bb->isAllLaneActive() || inst->isWriteEnableInst() ) &&
+        ( !bb->isInSimdFlow() || inst->isWriteEnableInst() ) &&
         !inst->getPredicate() &&
         dst->getRegAccess() == Direct &&
         dst->getHorzStride() == 1 &&
@@ -2252,7 +2252,7 @@ bool HWConformity::fixMULInst( INST_LIST_ITER &i, G4_BB *bb )
             if (next_dst != NULL &&
                 (next_inst->getSaturate() ||
                 next_dst->getByteOffset() % GENX_GRF_REG_SIZ != 0 ||
-                (!bb->isAllLaneActive() && next_inst->isWriteEnableInst() == false) ||
+                (bb->isInSimdFlow() && next_inst->isWriteEnableInst() == false) ||
                 (next_dst &&
                 ((next_dst->getExecTypeSize() > G4_Type_Table[Type_D].byteSize) ||
                 isPreAssignedRegOffsetNonZero<G4_DstRegRegion>(next_dst)))))
@@ -5462,7 +5462,7 @@ void HWConformity::fixSADA2Inst(G4_BB* bb)
         G4_INST* src2Dst = NULL;
 
         int emask = inst->getMaskOption();
-        if (!bb->isAllLaneActive() &&
+        if (bb->isInSimdFlow() &&
             emask != InstOpt_WriteEnable &&
             inst->getMaskOffset() != 0)
         {
@@ -6442,7 +6442,7 @@ bool HWConformity::splitInstListForByteDst( INST_LIST_ITER it, G4_BB *bb, uint16
     // check if we can split the inst
     if( !canSplitByteDst( inst_op ) ||
          inst->getExecSize() == 1 ||
-        ( !bb->isAllLaneActive() && !inst->isWriteEnableInst() ) ||
+        ( bb->isInSimdFlow() && !inst->isWriteEnableInst() ) ||
         dst->getByteOffset() % extypesize != 0 ||
         dst->getHorzStride() != 1 ||
         extypesize != G4_Type_Table[Type_W].byteSize)
@@ -6486,7 +6486,7 @@ bool HWConformity::splitInstListForByteDst( INST_LIST_ITER it, G4_BB *bb, uint16
         }
         if( canSplit )
         {
-            if( !bb->isAllLaneActive() && !defInst->isWriteEnableInst() )
+            if( bb->isInSimdFlow() && !defInst->isWriteEnableInst() )
             {
                 canSplit = false;
             }
@@ -7806,7 +7806,7 @@ void HWConformity::fixPredCtrl(INST_LIST_ITER it, G4_BB* bb)
             //
             // if f0 happens to be < 16 elements we have to clear upper bits as well in case it has garbage values
             assert(!inst->getCondMod() && "currently don't handle an instruction with conditional modifier");
-            assert((inst->isWriteEnableInst() || bb->isAllLaneActive()) && "don't handle instruction in SIMD CF for now");
+            assert((inst->isWriteEnableInst() || !bb->isInSimdFlow()) && "don't handle instruction in SIMD CF for now");
             G4_Declare* tmpFlag = builder.createTempFlag(1);
             G4_Type flagType = flagDcl->getNumberFlagElements() == 32 ? Type_UD : Type_UW;
             uint32_t allOneMask = (uint32_t) ((1ULL << flagDcl->getNumberFlagElements()) - 1);