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Synchronization between branches
---------------------------
1 parent 10d81ca commit 894e8de

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-260
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‎IGC/Compiler/tests/EmitVISAPass/vectorizer-vector-emission-exp2.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; UNSUPPORTED: system-windows
2-
; REQUIRES: pvc-supported, regkeys
2+
; REQUIRES: regkeys
33

44
; RUN: igc_opt -S -dce -platformpvc -rev-id B -has-emulated-64-bit-insts -igc-emit-visa --regkey=DumpVISAASMToConsole=1 -simd-mode 16 < %s | FileCheck %s
55

‎IGC/Compiler/tests/EmitVISAPass/vectorizer-vector-emission-fadd.ll‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,18 @@
1-
; REQUIRES: pvc-supported, regkeys
1+
; REQUIRES: regkeys
22

33
; RUN: igc_opt -S -dce -platformpvc -rev-id B -has-emulated-64-bit-insts -igc-emit-visa --regkey=DumpVISAASMToConsole=1 -simd-mode 16 < %s | FileCheck %s
44

5-
; CHECK: .decl vectorized_phi v_type=G type=f num_elts=128 align=wordx32
6-
; CHECK: .decl vector v_type=G type=f num_elts=8 align=dword
5+
; CHECK: .decl tmp15 v_type=G type=f num_elts=128 align=wordx32
6+
; CHECK: .decl tmp16 v_type=G type=f num_elts=8 align=dword
77

8-
; CHECK: add (M1, 16) vectorized_phi(0,0)<1> vector(0,0)<0;1,0> vectorized_phi(0,0)<1;1,0>
9-
; CHECK: add (M1, 16) vectorized_phi(1,0)<1> vector(0,1)<0;1,0> vectorized_phi(1,0)<1;1,0>
10-
; CHECK: add (M1, 16) vectorized_phi(2,0)<1> vector(0,2)<0;1,0> vectorized_phi(2,0)<1;1,0>
11-
; CHECK: add (M1, 16) vectorized_phi(3,0)<1> vector(0,3)<0;1,0> vectorized_phi(3,0)<1;1,0>
12-
; CHECK: add (M1, 16) vectorized_phi(4,0)<1> vector(0,4)<0;1,0> vectorized_phi(4,0)<1;1,0>
13-
; CHECK: add (M1, 16) vectorized_phi(5,0)<1> vector(0,5)<0;1,0> vectorized_phi(5,0)<1;1,0>
14-
; CHECK: add (M1, 16) vectorized_phi(6,0)<1> vector(0,6)<0;1,0> vectorized_phi(6,0)<1;1,0>
15-
; CHECK: add (M1, 16) vectorized_phi(7,0)<1> vector(0,7)<0;1,0> vectorized_phi(7,0)<1;1,0>
8+
; CHECK: add (M1, 16) tmp15(0,0)<1> tmp16(0,0)<0;1,0> tmp15(0,0)<1;1,0>
9+
; CHECK: add (M1, 16) tmp15(1,0)<1> tmp16(0,1)<0;1,0> tmp15(1,0)<1;1,0>
10+
; CHECK: add (M1, 16) tmp15(2,0)<1> tmp16(0,2)<0;1,0> tmp15(2,0)<1;1,0>
11+
; CHECK: add (M1, 16) tmp15(3,0)<1> tmp16(0,3)<0;1,0> tmp15(3,0)<1;1,0>
12+
; CHECK: add (M1, 16) tmp15(4,0)<1> tmp16(0,4)<0;1,0> tmp15(4,0)<1;1,0>
13+
; CHECK: add (M1, 16) tmp15(5,0)<1> tmp16(0,5)<0;1,0> tmp15(5,0)<1;1,0>
14+
; CHECK: add (M1, 16) tmp15(6,0)<1> tmp16(0,6)<0;1,0> tmp15(6,0)<1;1,0>
15+
; CHECK: add (M1, 16) tmp15(7,0)<1> tmp16(0,7)<0;1,0> tmp15(7,0)<1;1,0>
1616

1717
define spir_kernel void @blam(half addrspace(1)* %arg, half addrspace(1)* %arg1, half addrspace(1)* %arg2, float %arg3, i8 addrspace(1)* %arg4, float addrspace(1)* %arg5, <8 x i32> %arg6, <8 x i32> %arg7, i8* %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13) {
1818
bb:

‎IGC/Compiler/tests/EmitVISAPass/vectorizer-vector-emission-fdiv.ll‎

Lines changed: 59 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1,69 +1,76 @@
1-
; REQUIRES: pvc-supported, regkeys
1+
; UNSUPPORTED: system-windows
2+
; REQUIRES: regkeys
23

3-
; RUN: igc_opt -S -dce -platformpvc -rev-id B -has-emulated-64-bit-insts -igc-emit-visa --regkey=DumpVISAASMToConsole=1 -simd-mode 16 < %s | FileCheck %s
4+
; RUN: igc_opt -S -dce -platformpvc -rev-id B -has-emulated-64-bit-insts -igc-emit-visa --regkey=DumpVISAASMToConsole=1 --regkey=VectorizerUniformValueVectorizationEnabled=0 -simd-mode 16 < %s | FileCheck %s
45

5-
; CHECK: .decl vectorized_binary378 v_type=G type=f num_elts=8 align=dword
6-
; CHECK: .decl V0035 v_type=G type=f num_elts=8 align=wordx32
7-
; CHECK: .decl vectorized_binary402 v_type=G type=f num_elts=128 align=wordx32
8-
; CHECK: .decl V0036 v_type=G type=f num_elts=8 align=wordx32
6+
; CHECK: .decl vectorized_phi1095 v_type=G type=f num_elts=8 align=dword
7+
; CHECK: .decl vectorized_phi1116 v_type=G type=f num_elts=8 align=dword
8+
; CHECK: .decl vector1029 v_type=G type=f num_elts=8 align=dword
9+
; CHECK: .decl vector1052 v_type=G type=f num_elts=8 align=dword
910

10-
; CHECK: inv (M1_NM, 1) vectorized_binary378(0,0)<1> V0035(0,0)<0;1,0>
11-
; CHECK: inv (M1_NM, 1) vectorized_binary378(0,1)<1> V0035(0,1)<0;1,0>
12-
; CHECK: inv (M1_NM, 1) vectorized_binary378(0,2)<1> V0035(0,2)<0;1,0>
13-
; CHECK: inv (M1_NM, 1) vectorized_binary378(0,3)<1> V0035(0,3)<0;1,0>
14-
; CHECK: inv (M1_NM, 1) vectorized_binary378(0,4)<1> V0035(0,4)<0;1,0>
15-
; CHECK: inv (M1_NM, 1) vectorized_binary378(0,5)<1> V0035(0,5)<0;1,0>
16-
; CHECK: inv (M1_NM, 1) vectorized_binary378(0,6)<1> V0035(0,6)<0;1,0>
17-
; CHECK: inv (M1_NM, 1) vectorized_binary378(0,7)<1> V0035(0,7)<0;1,0>
18-
; CHECK: div (M1, 16) vectorized_binary402(0,0)<1> V0032(0,0)<1;1,0> V0036(0,0)<0;1,0>
19-
; CHECK: div (M1, 16) vectorized_binary402(1,0)<1> V0032(1,0)<1;1,0> V0036(0,1)<0;1,0>
20-
; CHECK: div (M1, 16) vectorized_binary402(2,0)<1> V0032(2,0)<1;1,0> V0036(0,2)<0;1,0>
21-
; CHECK: div (M1, 16) vectorized_binary402(3,0)<1> V0032(3,0)<1;1,0> V0036(0,3)<0;1,0>
22-
; CHECK: div (M1, 16) vectorized_binary402(4,0)<1> V0032(4,0)<1;1,0> V0036(0,4)<0;1,0>
23-
; CHECK: div (M1, 16) vectorized_binary402(5,0)<1> V0032(5,0)<1;1,0> V0036(0,5)<0;1,0>
24-
; CHECK: div (M1, 16) vectorized_binary402(6,0)<1> V0032(6,0)<1;1,0> V0036(0,6)<0;1,0>
25-
; CHECK: div (M1, 16) vectorized_binary402(7,0)<1> V0032(7,0)<1;1,0> V0036(0,7)<0;1,0>
2611

27-
define spir_kernel void @_attn_fwd(half addrspace(1)* %0, half addrspace(1)* %1, half addrspace(1)* %2, float %3, i8 addrspace(1)* %4, float addrspace(1)* %5, <8 x i32> %r0) {
12+
; CHECK: div (M1_NM, 1) vectorized_binary1096(0,0)<1> vectorized_phi1095(0,0)<0;1,0> vector1029(0,0)<0;1,0>
13+
; CHECK: div (M1_NM, 1) vectorized_binary1096(0,1)<1> vectorized_phi1095(0,1)<0;1,0> vector1029(0,1)<0;1,0>
14+
; CHECK: div (M1_NM, 1) vectorized_binary1096(0,2)<1> vectorized_phi1095(0,2)<0;1,0> vector1029(0,2)<0;1,0>
15+
; CHECK: div (M1_NM, 1) vectorized_binary1096(0,3)<1> vectorized_phi1095(0,3)<0;1,0> vector1029(0,3)<0;1,0>
16+
; CHECK: div (M1_NM, 1) vectorized_binary1096(0,4)<1> vectorized_phi1095(0,4)<0;1,0> vector1029(0,4)<0;1,0>
17+
; CHECK: div (M1_NM, 1) vectorized_binary1096(0,5)<1> vectorized_phi1095(0,5)<0;1,0> vector1029(0,5)<0;1,0>
18+
; CHECK: div (M1_NM, 1) vectorized_binary1096(0,6)<1> vectorized_phi1095(0,6)<0;1,0> vector1029(0,6)<0;1,0>
19+
; CHECK: div (M1_NM, 1) vectorized_binary1096(0,7)<1> vectorized_phi1095(0,7)<0;1,0> vector1029(0,7)<0;1,0>
20+
; CHECK: div (M1_NM, 1) vectorized_binary1117(0,0)<1> vectorized_phi1116(0,0)<0;1,0> vector1052(0,0)<0;1,0>
21+
; CHECK: div (M1_NM, 1) vectorized_binary1117(0,1)<1> vectorized_phi1116(0,1)<0;1,0> vector1052(0,1)<0;1,0>
22+
; CHECK: div (M1_NM, 1) vectorized_binary1117(0,2)<1> vectorized_phi1116(0,2)<0;1,0> vector1052(0,2)<0;1,0>
23+
; CHECK: div (M1_NM, 1) vectorized_binary1117(0,3)<1> vectorized_phi1116(0,3)<0;1,0> vector1052(0,3)<0;1,0>
24+
; CHECK: div (M1_NM, 1) vectorized_binary1117(0,4)<1> vectorized_phi1116(0,4)<0;1,0> vector1052(0,4)<0;1,0>
25+
; CHECK: div (M1_NM, 1) vectorized_binary1117(0,5)<1> vectorized_phi1116(0,5)<0;1,0> vector1052(0,5)<0;1,0>
26+
; CHECK: div (M1_NM, 1) vectorized_binary1117(0,6)<1> vectorized_phi1116(0,6)<0;1,0> vector1052(0,6)<0;1,0>
27+
; CHECK: div (M1_NM, 1) vectorized_binary1117(0,7)<1> vectorized_phi1116(0,7)<0;1,0> vector1052(0,7)<0;1,0>
28+
29+
source_filename = "reduced.ll"
30+
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32"
31+
target triple = "spir64-unknown-unknown"
32+
33+
define spir_kernel void @_attn_fwd(half addrspace(1)* %0, half addrspace(1)* %1, half addrspace(1)* %2, float %3, i8 addrspace(1)* %4, float addrspace(1)* %5, <8 x i32> %r0, <8 x i32> %payloadHeader, i32 %bufferOffset, i32 %bufferOffset1, i32 %bufferOffset2, i32 %bufferOffset3, i32 %bufferOffset4) {
2834
br label %._crit_edge
2935

30-
._crit_edge: ; preds = %._crit_edge, %6
31-
%7 = call <8 x float> @llvm.genx.GenISA.sub.group.dpas.v8f32.v8f32.v8i16.v8i32(<8 x float> zeroinitializer, <8 x i16> zeroinitializer, <8 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0, i1 false)
32-
br i1 false, label %._crit_edge, label %8
36+
._crit_edge: ; preds = %._crit_edge.._crit_edge_crit_edge, %6
37+
%vectorized_phi1095 = phi <8 x float> [ zeroinitializer, %6 ], [ %vectorized_binary1105, %._crit_edge.._crit_edge_crit_edge ]
38+
%vectorized_phi1116 = phi <8 x float> [ zeroinitializer, %6 ], [ %vectorized_binary1126, %._crit_edge.._crit_edge_crit_edge ]
39+
%vector1029 = insertelement <8 x float> zeroinitializer, float 0.000000e+00, i64 0
40+
%vector1052 = insertelement <8 x float> zeroinitializer, float 0.000000e+00, i64 0
41+
%vectorized_binary1096 = fdiv <8 x float> %vectorized_phi1095, %vector1029
42+
%vectorized_binary1117 = fdiv <8 x float> %vectorized_phi1116, %vector1052
43+
%vectorized_binary1105 = fadd <8 x float> %vectorized_binary1096, zeroinitializer
44+
%vectorized_binary1126 = fadd <8 x float> %vectorized_binary1117, zeroinitializer
45+
br i1 false, label %._crit_edge.._crit_edge_crit_edge, label %7
3346

34-
8: ; preds = %._crit_edge
35-
%vectorized_binary378 = fdiv <8 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, zeroinitializer
36-
%vectorized_binary402 = fdiv <8 x float> %7, zeroinitializer
37-
%9 = bitcast <8 x float> %vectorized_binary378 to <8 x i32>
38-
call void @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i1 false, i1 false, i32 0, <8 x i32> %9)
39-
%10 = bitcast <8 x float> %vectorized_binary402 to <8 x i32>
40-
call void @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i1 false, i1 false, i32 0, <8 x i32> %10)
47+
._crit_edge.._crit_edge_crit_edge: ; preds = %._crit_edge
48+
br label %._crit_edge
49+
50+
7: ; preds = %._crit_edge
51+
%.assembled.vect934 = bitcast <8 x float> %vectorized_binary1126 to <8 x i32>
52+
call void @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 32, i32 1, i32 1, i32 1, i1 false, i1 false, i32 0, <8 x i32> %.assembled.vect934)
53+
%.assembled.vect950 = bitcast <8 x float> %vectorized_binary1105 to <8 x i32>
54+
call void @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 32, i32 1, i32 1, i32 1, i1 false, i1 false, i32 0, <8 x i32> %.assembled.vect950)
4155
ret void
4256
}
4357

44-
declare <8 x float> @llvm.genx.GenISA.sub.group.dpas.v8f32.v8f32.v8i16.v8i32(<8 x float>, <8 x i16>, <8 x i32>, i32, i32, i32, i32, i1)
45-
4658
declare void @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32, <8 x i32>)
4759

4860
; uselistorder directives
4961
uselistorder void (i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32, <8 x i32>)* @llvm.genx.GenISA.LSC2DBlockWrite.v8i32, { 1, 0 }
5062

5163
!igc.functions = !{!0}
64+
!IGCMetadata = !{!4}
5265

53-
!0 = !{void (half addrspace(1)*, half addrspace(1)*, half addrspace(1)*, float, i8 addrspace(1)*, float addrspace(1)*, <8 x i32>, <8 x i32>, i32, i32, i32, i32, i32)* bitcast (void (half addrspace(1)*, half addrspace(1)*, half addrspace(1)*, float, i8 addrspace(1)*, float addrspace(1)*, <8 x i32>)* @_attn_fwd to void (half addrspace(1)*, half addrspace(1)*, half addrspace(1)*, float, i8 addrspace(1)*, float addrspace(1)*, <8 x i32>, <8 x i32>, i32, i32, i32, i32, i32)*), !1}
54-
!1 = !{!2, !3, !16}
55-
!2 = !{!"function_type", i32 0}
56-
!3 = !{!"implicit_arg_desc", !4, !5, !6, !8, !10, !12, !14}
57-
!4 = !{i32 0}
58-
!5 = !{i32 1}
59-
!6 = !{i32 15, !7}
60-
!7 = !{!"explicit_arg_num", i32 0}
61-
!8 = !{i32 15, !9}
62-
!9 = !{!"explicit_arg_num", i32 1}
63-
!10 = !{i32 15, !11}
64-
!11 = !{!"explicit_arg_num", i32 2}
65-
!12 = !{i32 15, !13}
66-
!13 = !{!"explicit_arg_num", i32 4}
67-
!14 = !{i32 15, !15}
68-
!15 = !{!"explicit_arg_num", i32 5}
69-
!16 = !{!"sub_group_size", i32 16}
66+
!0 = distinct !{void (half addrspace(1)*, half addrspace(1)*, half addrspace(1)*, float, i8 addrspace(1)*, float addrspace(1)*, <8 x i32>, <8 x i32>, i32, i32, i32, i32, i32)* @_attn_fwd, !1}
67+
!1 = distinct !{!2, !3}
68+
!2 = distinct !{!"function_type", i32 0}
69+
!3 = distinct !{!"sub_group_size", i32 16}
70+
!4 = distinct !{!"ModuleMD", !5}
71+
!5 = distinct !{!"FuncMD", !6, !7}
72+
!6 = distinct !{!"FuncMDMap[0]", void (half addrspace(1)*, half addrspace(1)*, half addrspace(1)*, float, i8 addrspace(1)*, float addrspace(1)*, <8 x i32>, <8 x i32>, i32, i32, i32, i32, i32)* @_attn_fwd}
73+
!7 = distinct !{!"FuncMDValue[0]", !8}
74+
!8 = distinct !{!"resAllocMD", !9}
75+
!9 = distinct !{!"argAllocMDList", !10}
76+
!10 = distinct !{!"argAllocMDListVec[0]"}

‎IGC/Compiler/tests/EmitVISAPass/vectorizer-vector-emission-fmad-first-operand-fixed-constant-vector.ll‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,8 @@
66
;
77
;============================ end_copyright_notice =============================
88

9-
; REQUIRES: regkeys, pvc-supported
9+
; UNSUPPORTED: system-windows
10+
; REQUIRES: regkeys
1011

1112
; RUN: igc_opt -S -dce -platformpvc -rev-id B -has-emulated-64-bit-insts -igc-emit-visa --regkey=DumpVISAASMToConsole=1 -simd-mode 16 < %s | FileCheck %s
1213

‎IGC/Compiler/tests/EmitVISAPass/vectorizer-vector-emission-fmul.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; UNSUPPORTED: system-windows
2-
; REQUIRES: pvc-supported, regkeys
2+
; REQUIRES: regkeys
33

44
; RUN: igc_opt -S -dce -platformpvc -rev-id B -has-emulated-64-bit-insts -igc-emit-visa --regkey=DumpVISAASMToConsole=1 -simd-mode 16 < %s | FileCheck %s
55

‎IGC/Compiler/tests/EmitVISAPass/vectorizer-vector-emission-fptrunc.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; UNSUPPORTED: system-windows
2-
; REQUIRES: pvc-supported, regkeys
2+
; REQUIRES: regkeys
33

44
; RUN: igc_opt -S -dce -platformpvc -rev-id B -has-emulated-64-bit-insts -igc-emit-visa --regkey=DumpVISAASMToConsole=1 -simd-mode 16 < %s | FileCheck %s
55

‎IGC/Compiler/tests/IGCVectorizer/vectorizer-test-binary-fmul.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
; REQUIRES: pvc-supported, regkeys
2-
; RUN: igc_opt -S --igc-vectorizer -dce --regkey=VectorizerEnablePartialVectorization=0 < %s 2>&1 | FileCheck %s
1+
; REQUIRES: regkeys
2+
; RUN: igc_opt -S --igc-vectorizer -dce --regkey=VectorizerAllowEXP2=0 --regkey=VectorizerEnablePartialVectorization=0 < %s 2>&1 | FileCheck %s
33

44
; CHECK: %vectorized_phi
55
; CHECK: %vector = insertelement <8 x float> undef

‎IGC/Compiler/tests/IGCVectorizer/vectorizer-test-exp2.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; REQUIRES: pvc-supported, regkeys
1+
; REQUIRES: regkeys
22
; RUN: igc_opt -S --igc-vectorizer -dce --regkey=VectorizerAllowEXP2=1 < %s 2>&1 | FileCheck %s
33

44
; CHECK: %vectorized_phi

‎IGC/Compiler/tests/IGCVectorizer/vectorizer-test-partial-vectorization.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
; REQUIRES: pvc-supported, regkeys
2-
; RUN: igc_opt -S --igc-vectorizer -dce --regkey=VectorizerEnablePartialVectorization=1 < %s 2>&1 | FileCheck %s
1+
; REQUIRES: regkeys, llvm-15-or-older
2+
; RUN: igc_opt -S --igc-vectorizer -dce --regkey=VectorizerAllowEXP2=0 --regkey=VectorizerEnablePartialVectorization=1 < %s 2>&1 | FileCheck %s
33

44
; CHECK: %vectorized_phi
55
; CHECK: [[vec_insert0:%vector.*]] = insertelement <8 x float> undef,

‎IGC/Compiler/tests/IGCVectorizer/vectorizer-test-ugly-chain.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; REQUIRES: pvc-supported, regkeys
1+
; REQUIRES: regkeys
22
; RUN: igc_opt -S --igc-vectorizer -dce --regkey=VectorizerEnablePartialVectorization=0 < %s 2>&1 | FileCheck %s
33

44
; CHECK: %vectorized_phi

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