Add missed llvm-14 pipeline passes

.

Author: igorban-intel

IGC/VectorCompiler/lib/GenXCodeGen/GenXTargetMachine.cpp

@@ -68,7 +68,10 @@ SPDX-License-Identifier: MIT
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Transforms/IPO.h"
 #include "llvm/Transforms/IPO/AlwaysInliner.h"
+#include "llvm/Transforms/IPO/Annotation2Metadata.h"
+#include "llvm/Transforms/IPO/ForceFunctionAttrs.h"
 #include "llvm/Transforms/IPO/GlobalDCE.h"
+#include "llvm/Transforms/IPO/InferFunctionAttrs.h"
 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
 #include "llvm/Transforms/InstCombine/InstCombine.h"
 #include "llvm/Transforms/Scalar.h"
@@ -83,6 +86,7 @@ SPDX-License-Identifier: MIT
 #include "llvm/Transforms/Scalar/LoopIdiomRecognize.h"
 #include "llvm/Transforms/Scalar/LoopRotation.h"
 #include "llvm/Transforms/Scalar/LoopUnrollPass.h"
+#include "llvm/Transforms/Scalar/LowerExpectIntrinsic.h"
 #include "llvm/Transforms/Scalar/Reassociate.h"
 #include "llvm/Transforms/Scalar/SROA.h"
 #include "llvm/Transforms/Scalar/SimplifyCFG.h"
@@ -1073,6 +1077,16 @@ void GenXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
     // Lower aggr copies.
     PM.addPass(createModuleToFunctionPassAdaptor(GenXLowerAggrCopiesPass()));
 
+    // Standard set of passes called in llvm-14
+    PM.addPass(createModuleToFunctionPassAdaptor(LowerExpectIntrinsicPass()));
+    PM.addPass(createModuleToFunctionPassAdaptor(SimplifyCFGPass()));
+    PM.addPass(
+        createModuleToFunctionPassAdaptor(SROAPass(SROAOptions::ModifyCFG)));
+    PM.addPass(createModuleToFunctionPassAdaptor(EarlyCSEPass(true)));
+    PM.addPass(Annotation2MetadataPass());
+    PM.addPass(ForceFunctionAttrsPass());
+    PM.addPass(InferFunctionAttrsPass());
+
     // Packetize.
     PM.addPass(GenXLegalizeGVLoadUsesPass());
 #ifndef NDEBUG

IGC/ocloc_tests/VC/PrintfResolution/llvm16_pipeline.ll

@@ -0,0 +1,26 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2025 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; REQUIRES: regkeys, pvc-supported, llvm-16-plus
+; RUN: llvm-as %s -o %t.bc
+; RUN: ocloc -device pvc -llvm_input -options "-vc-codegen -igc_opts 'ShaderDumpEnable=1, PrintToConsole=1'" -file %t.bc 2>&1 | FileCheck %s
+
+; CHECK: _after_ir_adaptors.ll
+; CHECK: spir_func i32 @_Z18__spirv_ocl_printfPciiiiii
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024"
+target triple = "spir64-unknown-unknown"
+
+define spir_kernel void @foo() {
+entry:
+  store <4 x i32>* null, <4 x i32>** null, align 4294967296
+  %call.i18 = call spir_func i32 @_Z18__spirv_ocl_printfPciiiiii(i8* null)
+  ret void
+}
+
+declare spir_func i32 @_Z18__spirv_ocl_printfPciiiiii(i8*)

IGC/ocloc_tests/lit.cfg.py

@@ -85,6 +85,9 @@ def get_available_devices(tool_path, ld_path):
   config.available_features.add('spirv-as')
   llvm_config.add_tool_substitutions([ToolSubst('spirv-as', unresolved='fatal')], tool_dirs)
 
+if int(config.llvm_version_major) >= 16:
+  config.available_features.add('llvm-16-plus')
+
 if config.llvm_spirv_enabled:
   config.available_features.add('llvm-spirv')
   llvm_config.add_tool_substitutions([ToolSubst('llvm-spirv', unresolved='fatal')], tool_dirs)