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bcheng0127gfxbot
bcheng0127
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Interanl feature
Change-Id: I31e68c0dba439054684f47c0ba41c59219784702
1 parent 87d61ef commit 8c4c498

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4 files changed

+47
-43
lines changed

4 files changed

+47
-43
lines changed

‎visa/Gen4_IR.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -828,6 +828,7 @@ G4_Type G4_INST::getExecType2() const
828828
uint16_t G4_INST::getMaskOffset()
829829
{
830830
unsigned maskOption = (this->getOption() & InstOpt_QuarterMasks);
831+
831832
switch(maskOption)
832833
{
833834
case InstOpt_NoOpt:

‎visa/GraphColor.cpp‎

Lines changed: 18 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -2539,7 +2539,7 @@ void GlobalRA::updateSubRegAlignment(unsigned char regFile, G4_SubReg_Align subA
25392539
else if (!areAllDefsNoMask(topdcl) &&
25402540
getAugmentationMask(topdcl) != AugmentationMasks::NonDefault)
25412541
{
2542-
dcl->setSubRegAlign(Sixteen_Word);
2542+
dcl->setSubRegAlign(subAlign);
25432543
}
25442544
}
25452545
}
@@ -2841,7 +2841,7 @@ void Augmentation::updateDstMask(G4_INST* inst, bool checkCmodOnly)
28412841
elemSize = 1;
28422842
}
28432843

2844-
startByte = (row * 32) + (subReg * elemSize);
2844+
startByte = (row * getGRFSize()) + (subReg * elemSize);
28452845

28462846
if (dst->isFlag())
28472847
{
@@ -4706,7 +4706,7 @@ void Augmentation::augmentIntfGraph()
47064706
#endif
47074707
gra.updateAlignment(G4_GRF, Even);
47084708
}
4709-
gra.updateSubRegAlignment(G4_GRF, Sixteen_Word);
4709+
gra.updateSubRegAlignment(G4_GRF, SUB_ALIGNMENT_GRFALIGN);
47104710
}
47114711

47124712
// Clear information calculated in this iteration of RA so
@@ -6115,7 +6115,7 @@ bool GraphColor::regAlloc(bool doBankConflictReduction,
61156115
//
61166116
if (dcl->getNumRows() > 1)
61176117
{
6118-
lrs[i]->getVar()->setSubRegAlignment(Sixteen_Word);
6118+
lrs[i]->getVar()->setSubRegAlignment(SUB_ALIGNMENT_GRFALIGN);
61196119
}
61206120
//
61216121
// single-row
@@ -6512,7 +6512,7 @@ void GraphColor::saveRegs(
65126512
0, 0, builder.rgnpool.createRegion(8, 8, 1), Type_UD);
65136513
unsigned messageLength = owordSize / 2;
65146514
G4_Declare *msgDcl = builder.createTempVar(messageLength * GENX_DATAPORT_IO_SZ,
6515-
Type_UD, Either, Sixteen_Word, StackCallStr);
6515+
Type_UD, Either, SUB_ALIGNMENT_GRFALIGN, StackCallStr);
65166516
msgDcl->getRegVar()->setPhyReg(regPool.getGreg(startReg), 0);
65176517
auto sendSrc2 = builder.createSrcRegRegion(Mod_src_undef, Direct, msgDcl->getRegVar(), 0, 0,
65186518
builder.rgnpool.createRegion(8, 8, 1), Type_UD);
@@ -6637,7 +6637,7 @@ void GraphColor::restoreRegs(
66376637

66386638
unsigned responseLength = ROUND(owordSize, 2) / 2;
66396639
G4_Declare *dstDcl = builder.createTempVar(responseLength * GENX_DATAPORT_IO_SZ,
6640-
Type_UD, Either, Sixteen_Word, GraphColor::StackCallStr);
6640+
Type_UD, Either, SUB_ALIGNMENT_GRFALIGN, GraphColor::StackCallStr);
66416641
dstDcl->getRegVar()->setPhyReg(regPool.getGreg(startReg), 0);
66426642
G4_DstRegRegion* postDst = builder.createDstRegRegion(Direct, dstDcl->getRegVar(), 0, 0, 1, (execSize > 8) ? Type_UW : Type_UD);
66436643
G4_SrcRegRegion* payload = builder.Create_Src_Opnd_From_Dcl(scratchRegDcl, builder.getRegionStride1());
@@ -7013,7 +7013,7 @@ void GraphColor::addCallerSaveRestoreCode()
70137013
{
70147014
std::ofstream optreport;
70157015
getOptReportStream(optreport, m_options);
7016-
optreport << "Caller save size: " << callerSaveRegCount * 32 <<
7016+
optreport << "Caller save size: " << callerSaveRegCount * getGRFSize() <<
70177017
" bytes for fcall at cisa id " <<
70187018
(*it)->back()->getCISAOff() << std::endl;
70197019
closeOptReportStream(optreport);
@@ -7143,7 +7143,7 @@ void GraphColor::addCalleeSaveRestoreCode()
71437143
{
71447144
std::ofstream optreport;
71457145
getOptReportStream(optreport, m_options);
7146-
optreport << "Callee save size: " << calleeSaveRegCount * 32 <<
7146+
optreport << "Callee save size: " << calleeSaveRegCount * getGRFSize() <<
71477147
" bytes" << std::endl;
71487148
closeOptReportStream(optreport);
71497149
}
@@ -10987,7 +10987,6 @@ void GraphColor::dumpRegisterPressure()
1098710987
}
1098810988
}
1098910989

10990-
1099110990
// FIXME: is any of this necessary? If they are they should be moved to HWConformity, is the concern
1099210991
// that new variables created by lvn/spill/remat may not honor alignment requirements?
1099310992
void GlobalRA::fixAlignment()
@@ -11001,13 +11000,14 @@ void GlobalRA::fixAlignment()
1100111000
{
1100211001
G4_RegVar* var = dst->getBase()->asRegVar();
1100311002
// dst register on sendin must be whole register aligned.
11003+
// NOTE THAT: The assumption is that the previous pass will set only SUB_ALIGNMENT_HALFGRFALIGN or whole GRF align
1100411004
if (inst->isSend() && dst->getRegAccess() == Direct) {
1100511005
if (!var->isPhyRegAssigned() &&
1100611006
(var->getDeclare()->getSubRegAlign() == Any ||
11007-
var->getDeclare()->getSubRegAlign() == Even_Word ||
11008-
var->getDeclare()->getSubRegAlign() == Eight_Word))
11007+
var->getDeclare()->getSubRegAlign() == Even_Word ||
11008+
var->getDeclare()->getSubRegAlign() == SUB_ALIGNMENT_HALFGRFALIGN))
1100911009
{
11010-
var->setSubRegAlignment(Sixteen_Word);
11010+
var->setSubRegAlignment(SUB_ALIGNMENT_GRFALIGN);
1101111011
}
1101211012
}
1101311013

@@ -11025,13 +11025,13 @@ void GlobalRA::fixAlignment()
1102511025
if (inst->isAccSrcInst())
1102611026
{
1102711027
if (var->getDeclare()->getRegFile() != G4_ADDRESS)
11028-
var->setSubRegAlignment(Sixteen_Word);
11028+
var->setSubRegAlignment(SUB_ALIGNMENT_GRFALIGN);
1102911029
else
11030-
var->setSubRegAlignment(Eight_Word);
11030+
var->setSubRegAlignment(SUB_ALIGNMENT_HALFGRFALIGN);
1103111031
}
11032-
else if (var->getSubRegAlignment() != Sixteen_Word)
11032+
else if (var->getSubRegAlignment() != SUB_ALIGNMENT_GRFALIGN)
1103311033
{
11034-
if (inst->opcode() == G4_movi)
11034+
if (inst->opcode() == G4_movi) //FIXME: restriction for movi, what about 64 bytes GRF
1103511035
{
1103611036
G4_Type dstType = dst->getType();
1103711037
switch (G4_Type_Table[dstType].byteSize)
@@ -11079,7 +11079,8 @@ void GlobalRA::fixAlignment()
1107911079

1108011080
G4_SubReg_Align dstSubAlign = var->getSubRegAlignment();
1108111081
if (dstSubAlign != Eight_Word &&
11082-
dstSubAlign != Sixteen_Word)
11082+
dstSubAlign != Sixteen_Word
11083+
)
1108311084
{
1108411085
for (unsigned j = 0; j < G4_MAX_SRCS; j++)
1108511086
{

‎visa/PhyRegUsage.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ void PhyRegUsage::markBusyForDclSplit(G4_RegFileKind kind,
9898
for (unsigned i = start_GRF; i < end_GRF; i++)
9999
{
100100
availableGregs[i] = false;
101-
availableSubRegs[i] = 0xffff0000; //Is this right?
101+
availableSubRegs[i] = 0xffff0000;
102102
}
103103

104104
if (end_sub_GRF)
@@ -244,7 +244,7 @@ int PhyRegUsage::findContiguousWords(
244244
int step = getStepAccordingSubAlign(subAlign);
245245
int startWord = 0;
246246

247-
for (int i = startWord; i + numWords <= 16; i += step)
247+
for (int i = startWord; i + numWords <= (int)G4_GRF_REG_SIZE; i += step)
248248
{
249249
uint32_t bitMask = getSubregBitMask(i, numWords);
250250
if ((bitMask & words) == bitMask)

‎visa/PhyRegUsage.h‎

Lines changed: 26 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -215,31 +215,31 @@ class PhyRegUsage
215215
void markBusyGRF(unsigned regNum,
216216
unsigned regOff,
217217
unsigned nunits,
218-
unsigned numRows)
219-
{
220-
MUST_BE_TRUE(numRows > 0 && nunits > 0, ERROR_INTERNAL_ARGUMENT);
218+
unsigned numRows)
219+
{
220+
MUST_BE_TRUE(numRows > 0 && nunits > 0, ERROR_INTERNAL_ARGUMENT);
221221

222-
MUST_BE_TRUE(regNum + numRows <= maxGRFCanBeUsed,
223-
ERROR_UNKNOWN);
222+
MUST_BE_TRUE(regNum + numRows <= maxGRFCanBeUsed,
223+
ERROR_UNKNOWN);
224224

225-
//
226-
// sub reg allocation (allocation unit is word)
227-
//
228-
if (numRows == 1 && regOff + nunits < G4_GRF_REG_SIZE)
229-
{
230-
availableGregs[regNum] = false;
231-
auto subregMask = getSubregBitMask(regOff, nunits);
232-
availableSubRegs[regNum] &= ~subregMask;
233-
}
234-
else // allocate whole registers
235-
{
236-
for (unsigned i = 0; i < numRows; i++)
237-
{
238-
availableGregs[regNum + i] = false;
239-
availableSubRegs[regNum + i] = 0xffff0000;
240-
}
241-
}
242-
}
225+
//
226+
// sub reg allocation (allocation unit is word)
227+
//
228+
if (numRows == 1 && regOff + nunits < G4_GRF_REG_SIZE)
229+
{
230+
availableGregs[regNum] = false;
231+
auto subregMask = getSubregBitMask(regOff, nunits);
232+
availableSubRegs[regNum] &= ~subregMask;
233+
}
234+
else // allocate whole registers
235+
{
236+
for (unsigned i = 0; i < numRows; i++)
237+
{
238+
availableGregs[regNum + i] = false;
239+
availableSubRegs[regNum + i] = 0xffff0000;
240+
}
241+
}
242+
}
243243

244244
void markBusyAddress(unsigned regNum,
245245
unsigned regOff,
@@ -288,7 +288,9 @@ class PhyRegUsage
288288
{
289289
MUST_BE_TRUE(num > 0 && start+num <= G4_GRF_REG_SIZE, "illegal number of words");
290290
uint32_t mask = ((1 << num) - 1) << start;
291-
MUST_BE_TRUE(mask <= 0xFFFFFFFF, "illegal subreg mask");
291+
292+
MUST_BE_TRUE(mask <= 0xFFFF, "illegal subreg mask");
293+
292294
return (uint32_t) mask;
293295
}
294296

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