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bcheng0127igcbot
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2 files changed

+20
-17
lines changed

2 files changed

+20
-17
lines changed

visa/Optimizer.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -828,6 +828,11 @@ void Optimizer::s0SubAfterRA() {
828828
return;
829829
}
830830

831+
// for 512 GRF mode, indirect-send is forbidden
832+
if (builder.kernel.getNumRegTotal() == 512) {
833+
return;
834+
}
835+
831836
kernel.fg.resetLocalDataFlowData();
832837
kernel.fg.localDataFlowAnalysis();
833838

visa/Passes/SRSubstitution.cpp

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -42,14 +42,15 @@ static bool regSortCompareBeforeRA(regMapBRA map1, regMapBRA map2) {
4242
void changeToIndirectSend(G4_INST *inst, G4_Declare *s0Var, int totalRegs, IR_Builder &builder) {
4343
// Change the send instruction to sendi
4444
G4_InstSend *Send = inst->asSendInst();
45-
G4_SendDescRaw *desc = Send->getMsgDescRaw();
46-
desc->setExtMessageLength(0);
47-
G4_Operand *msgDesc = inst->getSrc(2);
45+
G4_SendDescRaw *desc = Send->getMsgDescRaw();
46+
desc->setExtMessageLength(0);
47+
G4_Operand *msgDesc = inst->getSrc(2);
4848

49-
uint32_t descImm = (uint32_t)msgDesc->asImm()->getImm();
50-
descImm &= 0xE1FFFFFF; // clear bit 25:28
51-
descImm |= totalRegs << 25;
52-
G4_Imm *msgDescImm = builder.createImm(descImm, Type_UD);
49+
uint32_t descImm = (uint32_t)msgDesc->asImm()->getImm();
50+
descImm &= 0xE1FFFFFF; // clear bit 25:28
51+
descImm |= totalRegs << 25;
52+
G4_Imm *msgDescImm = builder.createImm(descImm, Type_UD);
53+
inst->setSrc(msgDescImm, 2);
5354

5455
// Replace source 0 with scalar register
5556
G4_SrcRegRegion *headerOpnd = builder.createSrcRegRegion(
@@ -59,7 +60,6 @@ void changeToIndirectSend(G4_INST *inst, G4_Declare *s0Var, int totalRegs, IR_Bu
5960

6061
inst->setSrc(headerOpnd, 0);
6162
inst->setSrc(payloadToUse, 1);
62-
inst->setSrc(msgDescImm, 2);
6363
}
6464

6565
// Check if current instruction is the candidate of sendi.
@@ -440,17 +440,12 @@ bool SRSubPassBeforeRA::isSRCandidateBeforeRA(G4_INST *inst,
440440
return false;
441441
}
442442

443-
//Don't do for EOT instruction first
444-
if (inst->isEOT()) {
445-
return false;
446-
}
447-
448443
if (!inst->isSplitSend()) {
449444
return false;
450445
}
451446

452447
G4_Operand *msgDesc = inst->getSrc(2);
453-
if (!msgDesc->isImm()) {
448+
if (!inst->asSendInst()->getMsgDesc() && !(msgDesc && msgDesc->isImm())) {
454449
return false;
455450
}
456451

@@ -513,7 +508,8 @@ bool SRSubPassBeforeRA::isSRCandidateBeforeRA(G4_INST *inst,
513508

514509
// Not GRF source
515510
if (!(src->getBase()->isRegVar() &&
516-
src->getBase()->asRegVar()->getDeclare()->getRegFile() == G4_GRF)) {
511+
(src->getBase()->asRegVar()->getDeclare()->getRegFile() == G4_GRF ||
512+
src->getBase()->asRegVar()->getDeclare()->getRegFile() == G4_INPUT))) {
517513
return false;
518514
}
519515

@@ -574,8 +570,10 @@ bool SRSubPassBeforeRA::isSRCandidateBeforeRA(G4_INST *inst,
574570
}
575571

576572
// It's not global define
577-
if (kernel.fg.globalOpndHT.isOpndGlobal(dstRgn)) {
578-
return false;
573+
if (!(builder.getIsKernel() && kernel.fg.getNumBB() == 1)) {
574+
if (kernel.fg.globalOpndHT.isOpndGlobal(dstRgn)) {
575+
return false;
576+
}
579577
}
580578

581579
return true;

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