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Add support for i4 datatype and i4 vector manipulation emulation
- Add support for i4 promotions and emulate i4 vector operations (extractelement, insertelement, shufflevector), - Split tests into i1 and i4 directories, - Add GenISA_Int4VectorUnpack, GenISA_Int4VectorPack which enables i4 vector operations Support for i4 & i4 vector operations was added by extenion SPV_INTEL_int4 https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_int4.html
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lines changed

‎IGC/AdaptorOCL/CMakeLists.txt‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ set(IGC_BUILD__SRC__AdaptorOCL
2020
"${CMAKE_CURRENT_SOURCE_DIR}/LowerInvokeSIMD.cpp"
2121
"${CMAKE_CURRENT_SOURCE_DIR}/ResolveConstExprCalls.cpp"
2222
"${CMAKE_CURRENT_SOURCE_DIR}/preprocess_spvir/PreprocessSPVIR.cpp"
23-
"${CMAKE_CURRENT_SOURCE_DIR}/preprocess_spvir/PromoteBools.cpp"
23+
"${CMAKE_CURRENT_SOURCE_DIR}/preprocess_spvir/PromoteSubByte.cpp"
2424
"${CMAKE_CURRENT_SOURCE_DIR}/preprocess_spvir/HandleSPIRVDecorations/HandleSpirvDecorationMetadata.cpp"
2525
)
2626

@@ -89,7 +89,7 @@ set(IGC_BUILD__HDR__AdaptorOCL
8989
"${CMAKE_CURRENT_SOURCE_DIR}/MoveStaticAllocas.h"
9090
"${CMAKE_CURRENT_SOURCE_DIR}/LowerInvokeSIMD.hpp"
9191
"${CMAKE_CURRENT_SOURCE_DIR}/ResolveConstExprCalls.h"
92-
"${CMAKE_CURRENT_SOURCE_DIR}/preprocess_spvir/PromoteBools.h"
92+
"${CMAKE_CURRENT_SOURCE_DIR}/preprocess_spvir/PromoteSubByte.h"
9393
"${CMAKE_CURRENT_SOURCE_DIR}/preprocess_spvir/HandleSPIRVDecorations/HandleSpirvDecorationMetadata.h"
9494
"${CMAKE_CURRENT_SOURCE_DIR}/preprocess_spvir/PreprocessSPVIR.h"
9595

‎IGC/AdaptorOCL/UnifyIROCL.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ SPDX-License-Identifier: MIT
115115
#include "MoveStaticAllocas.h"
116116
#include "preprocess_spvir/PreprocessSPVIR.h"
117117
#include "preprocess_spvir/ConvertUserSemanticDecoratorOnFunctions.h"
118-
#include "preprocess_spvir/PromoteBools.h"
118+
#include "preprocess_spvir/PromoteSubByte.h"
119119
#include "preprocess_spvir/HandleSPIRVDecorations/HandleSpirvDecorationMetadata.h"
120120
#include "LowerInvokeSIMD.hpp"
121121
#include "ResolveConstExprCalls.h"
@@ -276,7 +276,7 @@ static void CommonOCLBasedPasses(OpenCLProgramContext *pContext) {
276276

277277
IGCPassManager mpmSPIR(pContext, "Unify");
278278
mpmSPIR.add(new PreprocessSPVIR());
279-
mpmSPIR.add(new PromoteBools());
279+
mpmSPIR.add(new PromoteSubByte());
280280
mpmSPIR.add(new TypesLegalizationPass());
281281
mpmSPIR.add(new TargetLibraryInfoWrapperPass());
282282
mpmSPIR.add(new MetaDataUtilsWrapper(pMdUtils, pContext->getModuleMetaData()));

‎IGC/AdaptorOCL/preprocess_spvir/PromoteBools.cpp‎ renamed to ‎IGC/AdaptorOCL/preprocess_spvir/PromoteSubByte.cpp‎

Lines changed: 250 additions & 66 deletions
Large diffs are not rendered by default.

‎IGC/AdaptorOCL/preprocess_spvir/PromoteBools.h‎ renamed to ‎IGC/AdaptorOCL/preprocess_spvir/PromoteSubByte.h‎

Lines changed: 16 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ SPDX-License-Identifier: MIT
99
#pragma once
1010

1111
#include "common/LLVMWarningsPush.hpp"
12-
#include "llvmWrapper/IR/Module.h"
12+
#include "llvmWrapper/IR/DerivedTypes.h"
1313
#include <llvm/Pass.h>
1414
#include <llvm/IR/InstVisitor.h>
1515
#include <llvm/IR/IRBuilder.h>
@@ -24,14 +24,14 @@ SPDX-License-Identifier: MIT
2424
}
2525

2626
namespace IGC {
27-
class PromoteBools : public llvm::ModulePass, public llvm::InstVisitor<PromoteBools> {
27+
class PromoteSubByte : public llvm::ModulePass, public llvm::InstVisitor<PromoteSubByte> {
2828
public:
2929
static char ID;
3030

31-
PromoteBools();
32-
~PromoteBools() {}
31+
PromoteSubByte();
32+
~PromoteSubByte() {}
3333

34-
virtual llvm::StringRef getPassName() const override { return "PromoteBools"; }
34+
virtual llvm::StringRef getPassName() const override { return "PromoteSubByte"; }
3535

3636
virtual bool runOnModule(llvm::Module &module) override;
3737

@@ -44,14 +44,15 @@ class PromoteBools : public llvm::ModulePass, public llvm::InstVisitor<PromoteBo
4444

4545
private:
4646
bool changed;
47+
llvm::Module *M = nullptr;
4748

48-
llvm::Value *convertI1ToI8(llvm::Value *argument, llvm::IRBuilder<>& builder);
49+
llvm::Value *convertI1ToI8(llvm::Value *argument, llvm::IRBuilder<> &builder);
4950
llvm::Value *convertI1ToI8(llvm::Value *argument, llvm::Instruction *insertBefore);
50-
llvm::Value *convertI8ToI1(llvm::Value *argument, llvm::IRBuilder<>& builder);
51+
llvm::Value *convertI8ToI1(llvm::Value *argument, llvm::IRBuilder<> &builder);
5152
llvm::Value *convertI8ToI1(llvm::Value *argument, llvm::Instruction *insertBefore);
52-
llvm::Value *castTo(llvm::Value *value, llvm::Type *desiredType, llvm::IRBuilder<>& builder);
53+
llvm::Value *castTo(llvm::Value *value, llvm::Type *desiredType, llvm::IRBuilder<> &builder);
5354
llvm::Value *castTo(llvm::Value *value, llvm::Type *desiredType, llvm::Instruction *insertBefore);
54-
llvm::Value *castAggregate(llvm::Value *value, llvm::Type *desiredType, llvm::IRBuilder<>& builder);
55+
llvm::Value *castAggregate(llvm::Value *value, llvm::Type *desiredType, llvm::IRBuilder<> &builder);
5556

5657
void cleanUp(llvm::Module &module);
5758

@@ -92,7 +93,12 @@ class PromoteBools : public llvm::ModulePass, public llvm::InstVisitor<PromoteBo
9293
llvm::StoreInst *promoteStore(llvm::StoreInst *store);
9394
llvm::IntToPtrInst *promoteIntToPtr(llvm::IntToPtrInst *inttoptr);
9495
llvm::ExtractElementInst *promoteExtractElement(llvm::ExtractElementInst *extractElement);
95-
llvm::InsertElementInst *promoteInsertElement(llvm::InsertElementInst *insertElement);
96+
llvm::Value *promoteInsertElement(llvm::InsertElementInst *insertElement);
97+
llvm::Value *promoteShuffleVector(llvm::ShuffleVectorInst *shuffleVector);
98+
llvm::Value *promoteAndUnpackInt4Vector(llvm::Value *unpromotedInput, llvm::IRBuilder<> &builder);
99+
llvm::Value *packInt4Vector(llvm::Value *input, llvm::IRBuilder<> &builder);
100+
llvm::Constant *unpackConstantInt4Vector(llvm::Value *input, IGCLLVM::FixedVectorType *outputTy);
101+
llvm::Constant *packConstantInt4Vector(llvm::Value *input);
96102

97103
// Promoting values - helping vars
98104
llvm::DenseSet<llvm::PHINode *> visitedPHINodes;

‎IGC/Compiler/CISACodeGen/EmitVISAPass.cpp‎

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8731,6 +8731,12 @@ void EmitPass::EmitGenIntrinsicMessage(llvm::GenIntrinsicInst *inst) {
87318731
case GenISAIntrinsic::GenISA_srnd_hftobf8:
87328732
emitSrnd(inst);
87338733
break;
8734+
case GenISAIntrinsic::GenISA_Int4VectorUnpack:
8735+
emitInt4VectorUnpack(inst);
8736+
break;
8737+
case GenISAIntrinsic::GenISA_Int4VectorPack:
8738+
emitInt4VectorPack(inst);
8739+
break;
87348740
case GenISAIntrinsic::GenISA_uavSerializeAll:
87358741
case GenISAIntrinsic::GenISA_uavSerializeOnResID:
87368742
emitUAVSerialize();
@@ -21305,6 +21311,83 @@ void EmitPass::emitSrnd(llvm::GenIntrinsicInst *GII) {
2130521311
}
2130621312
}
2130721313

21314+
void EmitPass::emitInt4VectorUnpack(llvm::GenIntrinsicInst *GII) {
21315+
Value *input = GII->getOperand(0);
21316+
CVariable *cinput = GetSymbol(input);
21317+
21318+
uint16_t inputNum = cinput->GetNumberElement();
21319+
uint16_t dstNum = m_destination->GetNumberElement();
21320+
21321+
IGC_ASSERT_MESSAGE(cinput->IsUniform() == m_destination->IsUniform(),
21322+
"Int4VectorUnpack expects both input and destination to have the same IsUniform state.");
21323+
uint16_t execSize = cinput->IsUniform() ? 1 : numLanes(m_currShader->m_SIMDSize);
21324+
m_encoder->SetSimdSize(lanesToSIMDMode(execSize));
21325+
21326+
// Round up to a multiple of inputNum.
21327+
uint16_t dstNumRoundedUp = ((dstNum + inputNum - 1) / inputNum) * inputNum;
21328+
if (inputNum * 2 != dstNumRoundedUp || cinput->GetElemSize() != 1 || m_destination->GetElemSize() != 1) {
21329+
IGC_ASSERT_MESSAGE(false, "Unexpected arguments in emitInt4VectorUnpack");
21330+
return;
21331+
}
21332+
21333+
CVariable *immFour = m_currShader->ImmToVariable(4, ISA_TYPE_UB);
21334+
CVariable *immMask4Bit = m_currShader->ImmToVariable(0b1111, ISA_TYPE_UB);
21335+
21336+
for (int rowOffset = 0; rowOffset < inputNum; rowOffset += execSize) {
21337+
CVariable *row = m_currShader->GetNewAlias(cinput, ISA_TYPE_UB, rowOffset, execSize);
21338+
CVariable *dst0 = m_currShader->GetNewAlias(m_destination, ISA_TYPE_UB, rowOffset * 2, execSize);
21339+
m_encoder->And(dst0, row, immMask4Bit);
21340+
21341+
if (rowOffset * 2 + execSize < dstNum) {
21342+
CVariable *dst1 = m_currShader->GetNewAlias(m_destination, ISA_TYPE_UB, rowOffset * 2 + execSize, execSize);
21343+
m_encoder->Shr(dst1, row, immFour);
21344+
}
21345+
}
21346+
21347+
m_encoder->Push();
21348+
}
21349+
21350+
void EmitPass::emitInt4VectorPack(llvm::GenIntrinsicInst *GII) {
21351+
Value *input = GII->getOperand(0);
21352+
CVariable *cinput = GetSymbol(input);
21353+
21354+
uint16_t inputNum = cinput->GetNumberElement();
21355+
uint16_t dstNum = m_destination->GetNumberElement();
21356+
21357+
IGC_ASSERT_MESSAGE(cinput->IsUniform() == m_destination->IsUniform(),
21358+
"Int4VectorUnpack expects both input and destination to have the same IsUniform state.");
21359+
uint16_t execSize = m_destination->IsUniform() ? 1 : numLanes(m_currShader->m_SIMDSize);
21360+
m_encoder->SetSimdSize(lanesToSIMDMode(execSize));
21361+
21362+
// Round up to a multiple of dstNum.
21363+
uint16_t inputNumRoundedUp = ((inputNum + dstNum - 1) / dstNum) * dstNum;
21364+
if (inputNumRoundedUp != dstNum * 2 || cinput->GetElemSize() != 1 || m_destination->GetElemSize() != 1) {
21365+
IGC_ASSERT_MESSAGE(false, "Unexpected arguments in Int4VectorPack");
21366+
return;
21367+
}
21368+
21369+
CVariable *immFour = m_currShader->ImmToVariable(4, ISA_TYPE_UB);
21370+
21371+
for (int rowOffset = 0; rowOffset < dstNum; rowOffset += execSize) {
21372+
CVariable *row0 = m_currShader->GetNewAlias(cinput, ISA_TYPE_UB, rowOffset * 2, execSize);
21373+
CVariable *dst = m_currShader->GetNewAlias(m_destination, ISA_TYPE_UB, rowOffset, execSize);
21374+
21375+
// There is an edge case where we pack <3 x i8> into <2 x i8>.
21376+
// The missing 4th i8 cannot be loaded.
21377+
if (rowOffset * 2 + execSize < cinput->GetNumberElement()) {
21378+
CVariable *row1 = m_currShader->GetNewAlias(cinput, ISA_TYPE_UB, rowOffset * 2 + execSize, execSize);
21379+
CVariable *shl4 = m_currShader->GetNewVariable(row1, "shl4");
21380+
m_encoder->Shl(shl4, row1, immFour);
21381+
m_encoder->Or(dst, row0, shl4);
21382+
} else {
21383+
// Due to missing last element pass row0 directly to dst.
21384+
m_encoder->Copy(dst, row0);
21385+
}
21386+
}
21387+
21388+
m_encoder->Push();
21389+
}
21390+
2130821391
LSC_CACHE_OPTS EmitPass::translateLSCCacheControlsEnum(LSC_L1_L3_CC l1l3cc, bool isLoad,
2130921392
const Value *warningContextValue) const {
2131021393
if (!m_pCtx->platform.isSupportedLSCCacheControlsEnum(l1l3cc, isLoad)) {

‎IGC/Compiler/CISACodeGen/EmitVISAPass.hpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -575,6 +575,8 @@ class EmitPass : public llvm::FunctionPass {
575575
bool forceCacheCtrl(llvm::Instruction *vectorLdStInst = nullptr);
576576
uint32_t totalBytesToStoreOrLoad(llvm::Instruction *vectorLdStInst);
577577
void emitSrnd(llvm::GenIntrinsicInst *GII);
578+
void emitInt4VectorUnpack(llvm::GenIntrinsicInst *GII);
579+
void emitInt4VectorPack(llvm::GenIntrinsicInst *GII);
578580
void emitStaticConstantPatchValue(llvm::StaticConstantPatchIntrinsic *staticConstantPatch32);
579581
// Debug Built-Ins
580582
void emitStateRegID(uint32_t BitStart, uint32_t BitEnd);

‎IGC/Compiler/CISACodeGen/WIAnalysis.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1240,6 +1240,7 @@ WIAnalysis::WIDependancy WIAnalysisRunner::calculate_dep(const CallInst *inst) {
12401240
GII_id == GenISAIntrinsic::GenISA_2fto2bf || GII_id == GenISAIntrinsic::GenISA_dual_subslice_id ||
12411241
GII_id == GenISAIntrinsic::GenISA_hftobf8 || GII_id == GenISAIntrinsic::GenISA_bf8tohf ||
12421242
GII_id == GenISAIntrinsic::GenISA_srnd_ftohf || GII_id == GenISAIntrinsic::GenISA_srnd_hftobf8 ||
1243+
GII_id == GenISAIntrinsic::GenISA_Int4VectorUnpack || GII_id == GenISAIntrinsic::GenISA_Int4VectorPack ||
12431244
GII_id == GenISAIntrinsic::GenISA_hftohf8 || GII_id == GenISAIntrinsic::GenISA_hf8tohf ||
12441245
GII_id == GenISAIntrinsic::GenISA_ftotf32 || GII_id == GenISAIntrinsic::GenISA_GlobalBufferPointer ||
12451246
GII_id == GenISAIntrinsic::GenISA_LocalBufferPointer ||

‎IGC/Compiler/InitializePasses.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,7 @@ void initializeLowerInvokeSIMDPass(llvm::PassRegistry &);
281281
void initializeRemoveCodeAssumptionsPass(llvm::PassRegistry &);
282282
void initializePreprocessSPVIRPass(llvm::PassRegistry &);
283283
void initializeConvertUserSemanticDecoratorOnFunctionsPass(llvm::PassRegistry &);
284-
void initializePromoteBoolsPass(llvm::PassRegistry &);
284+
void initializePromoteSubBytePass(llvm::PassRegistry &);
285285
void initializeResolveConstExprCallsPass(llvm::PassRegistry &);
286286
void initializeHandleSpirvDecorationMetadataPass(llvm::PassRegistry &);
287287
void initializeNontemporalLoadsAndStoresInAssertPass(llvm::PassRegistry &);

‎IGC/Compiler/tests/EmitVISAPass/emit-int4-vector/pack-3-to-2-uniform.ll‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2025 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
; REQUIRES: regkeys
9+
;
10+
; RUN: igc_opt -platformbmg -igc-emit-visa -simd-mode 16 -inputrt -regkey DumpVISAASMToConsole -S %s | FileCheck %s
11+
; ------------------------------------------------
12+
; EmitVISAPass
13+
; ------------------------------------------------
14+
15+
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32"
16+
target triple = "spir64-unknown-unknown"
17+
18+
; CHECK-LABEL: .kernel "test"
19+
define spir_kernel void @test(i32 addrspace(1)* %src, i16 addrspace(1)* %dst, <8 x i32> %r0, <3 x i32> %globalOffset, i8 addrspace(1)* %indirectDataPointer, i8 addrspace(1)* %scratchPointer, i32 %bufferOffset, i32 %bufferOffset1) {
20+
entry:
21+
%loaded = load i32, i32 addrspace(1)* %src, align 4
22+
23+
; Extract first 3 bytes from loaded i32
24+
%loadedBytes = bitcast i32 %loaded to <4 x i8>
25+
%l0 = extractelement <4 x i8> %loadedBytes, i32 0
26+
%l1 = extractelement <4 x i8> %loadedBytes, i32 1
27+
%l2 = extractelement <4 x i8> %loadedBytes, i32 2
28+
29+
; Insert first 3 bytes into a <3 x i8> vector
30+
%i0 = insertelement <3 x i8> undef, i8 %l0, i32 0
31+
%i1 = insertelement <3 x i8> %i0, i8 %l1, i32 1
32+
%i2 = insertelement <3 x i8> %i1, i8 %l2, i32 2
33+
34+
; CHECK: shl (M1_NM, 1) [[SHIFTED1:[A-z0-9]*]](0,0)<1> [[LOADED:[A-z0-9]*]](0,1)<0;1,0> 0x4:ub
35+
; CHECK: or (M1_NM, 1) [[PACKED:[A-z0-9]*]](0,0)<1> [[LOADED]](0,0)<0;1,0> [[SHIFTED1]](0,0)<0;1,0>
36+
; CHECK-NOT: shl
37+
; CHECK-NOT: or
38+
; CHECK: mov (M1_NM, 1) [[PACKED]](0,1)<1> [[LOADED]](0,2)<0;1,0>
39+
%packed = call <2 x i8> @llvm.genx.GenISA.Int4VectorPack.v2i8.v3i8(<3 x i8> %i2)
40+
41+
; Store the packed result
42+
%packedCast = bitcast <2 x i8> %packed to i16
43+
store i16 %packedCast, i16 addrspace(1)* %dst, align 2
44+
ret void
45+
}
46+
47+
declare <2 x i8> @llvm.genx.GenISA.Int4VectorPack.v2i8.v3i8(<3 x i8>)
48+
49+
!igc.functions = !{!3}
50+
!3 = !{void (i32 addrspace(1)*, i16 addrspace(1)*, <8 x i32>, <3 x i32>, i8 addrspace(1)*, i8 addrspace(1)*, i32, i32)* @test, !4}
51+
!4 = !{!5, !6}
52+
!5 = !{!"function_type", i32 0}
53+
!6 = !{!"implicit_arg_desc", !7, !8, !9, !10, !11, !13}
54+
!7 = !{i32 0}
55+
!8 = !{i32 2}
56+
!9 = !{i32 62}
57+
!10 = !{i32 63}
58+
!11 = !{i32 15, !12}
59+
!12 = !{!"explicit_arg_num", i32 0}
60+
!13 = !{i32 15, !14}
61+
!14 = !{!"explicit_arg_num", i32 1}

‎IGC/Compiler/tests/EmitVISAPass/emit-int4-vector/pack-4-to-2.ll‎

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2025 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
; REQUIRES: regkeys
9+
;
10+
; RUN: igc_opt -platformbmg -igc-emit-visa -simd-mode 16 -inputrt -regkey DumpVISAASMToConsole -S %s | FileCheck %s
11+
; ------------------------------------------------
12+
; EmitVISAPass
13+
; ------------------------------------------------
14+
15+
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32"
16+
target triple = "spir64-unknown-unknown"
17+
18+
; CHECK-LABEL: .kernel "test"
19+
define spir_kernel void @test(i32 addrspace(1)* %src, i16 addrspace(1)* %dst, <8 x i32> %r0, <3 x i32> %globalOffset, <3 x i32> %enqueuedLocalSize, i16 %localIdX, i16 %localIdY, i16 %localIdZ, i8 addrspace(1)* %indirectDataPointer, i8 addrspace(1)* %scratchPointer, i32 %bufferOffset, i32 %bufferOffset1) {
20+
entry:
21+
; Compute offsetted pointers based on local ID
22+
%id = zext i16 %localIdX to i64
23+
%srcInt = ptrtoint i32 addrspace(1)* %src to i64
24+
%id2 = shl i64 %id, 2
25+
%srcIntOffsetted = add i64 %id2, %srcInt
26+
%dstInt = ptrtoint i16 addrspace(1)* %dst to i64
27+
%id1 = shl i64 %id, 1
28+
%dstIntOffsetted = add i64 %id1, %dstInt
29+
%srcOffsetted = inttoptr i64 %srcIntOffsetted to i32 addrspace(1)*
30+
%dstOffsetted = inttoptr i64 %dstIntOffsetted to i16 addrspace(1)*
31+
32+
; Load src and cast it to <4 x i8>
33+
%loaded = load i32, i32 addrspace(1)* %srcOffsetted, align 4
34+
%loadedCast = bitcast i32 %loaded to <4 x i8>
35+
36+
; CHECK: shl (M1, 16) [[SHIFTED1:[A-z0-9]*]](0,0)<1> [[LOADED:[A-z0-9]*]](0,16)<1;1,0> 0x4:ub
37+
; CHECK: or (M1, 16) [[PACKED:[A-z0-9]*]](0,0)<1> [[LOADED]](0,0)<1;1,0> [[SHIFTED1]](0,0)<1;1,0>
38+
; CHECK: shl (M1, 16) [[SHIFTED2:[A-z0-9]*]](0,0)<1> [[LOADED]](0,48)<1;1,0> 0x4:ub
39+
; CHECK: or (M1, 16) [[PACKED]](0,16)<1> [[LOADED]](0,32)<1;1,0> [[SHIFTED2]](0,0)<1;1,0>
40+
%packed = call <2 x i8> @llvm.genx.GenISA.Int4VectorPack.v2i8.v4i8(<4 x i8> %loadedCast)
41+
42+
; Store the packed result
43+
%packedCast = bitcast <2 x i8> %packed to i16
44+
store i16 %packedCast, i16 addrspace(1)* %dstOffsetted, align 2
45+
ret void
46+
}
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declare <2 x i8> @llvm.genx.GenISA.Int4VectorPack.v2i8.v4i8(<4 x i8>)
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!igc.functions = !{!3}
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!3 = !{void (i32 addrspace(1)*, i16 addrspace(1)*, <8 x i32>, <3 x i32>, <3 x i32>, i16, i16, i16, i8 addrspace(1)*, i8 addrspace(1)*, i32, i32)* @test, !4}
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!4 = !{!5, !6}
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!5 = !{!"function_type", i32 0}
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!6 = !{!"implicit_arg_desc", !7, !8, !9, !10, !11, !12, !13, !14, !15, !17}
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!7 = !{i32 0}
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!8 = !{i32 2}
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!9 = !{i32 7}
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!10 = !{i32 8}
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!11 = !{i32 9}
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!12 = !{i32 10}
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!13 = !{i32 62}
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!14 = !{i32 63}
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!15 = !{i32 15, !16}
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!16 = !{!"explicit_arg_num", i32 0}
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!17 = !{i32 15, !18}
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!18 = !{!"explicit_arg_num", i32 1}

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