Fix subroutine handling for intel_reqd_sub_group_size(32)

Previously, using `intel_reqd_sub_group_size(32)` on DG2 resulted in two
redundant SIMD32 call instructions being generated in vISA, which could
lead to unexpected issues. This change ensures that only a single SIMD32
call instruction is generated. All function arguments and return values
are now correctly passed using two SIMD16 instructions, eliminating
redundancy and improving

Author: aratajew

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -349,9 +349,8 @@ uint EmitPass::DecideInstanceAndSlice(const llvm::BasicBlock &blk, SDAG &sdag, b
   }
 
   if (CallInst *callInst = dyn_cast<CallInst>(sdag.m_root)) {
-    // Disable slicing for function calls
-    Function *F = dyn_cast<Function>(IGCLLVM::getCalledValue(callInst));
-    if (!F || F->hasFnAttribute("visaStackCall")) {
+    // Disable slicing for function calls (stackcalls and subroutines)
+    if (isUserFunctionCall(callInst)) {
       numInstance = 1;
       slicing = false;
     }
@@ -10712,7 +10711,7 @@ void EmitPass::emitCall(llvm::CallInst *inst) {
     // When both symbols are the same, then this argument passing has been
     // lifted to use a global vISA variable, just skip the copy.
     if (Dst != Src) {
-      emitCopyAll(Dst, Src, Arg.getType());
+      emitCopyAllInstances(Dst, Src, Arg.getType());
     }
   }
   m_currFuncHasSubroutine = true;
@@ -10723,7 +10722,7 @@ void EmitPass::emitCall(llvm::CallInst *inst) {
   if (!inst->use_empty()) {
     CVariable *Dst = GetSymbol(inst);
     CVariable *Src = m_currShader->getOrCreateReturnSymbol(F);
-    emitCopyAll(Dst, Src, inst->getType());
+    emitCopyAllInstances(Dst, Src, inst->getType());
   }
 }
 
@@ -10742,7 +10741,7 @@ void EmitPass::emitReturn(llvm::ReturnInst *inst) {
     if (!RetTy->isVoidTy()) {
       CVariable *Dst = m_currShader->getOrCreateReturnSymbol(F);
       CVariable *Src = GetSymbol(inst->getReturnValue());
-      emitCopyAll(Dst, Src, RetTy);
+      emitCopyAllInstances(Dst, Src, RetTy);
     }
 
     m_encoder->SubroutineRet(nullptr, F);
@@ -19167,6 +19166,13 @@ void EmitPass::emitCopyAll(CVariable *Dst, CVariable *Src, llvm::Type *Ty) {
   }
 }
 
+void EmitPass::emitCopyAllInstances(CVariable *Dst, CVariable *Src, llvm::Type *type) {
+  for (uint instance = 0; instance < Dst->GetNumberInstance(); instance++) {
+    m_encoder->SetSecondHalf(instance == 1 ? true : false);
+    emitCopyAll(Dst, Src, type);
+  }
+}
+
 void EmitPass::emitSqrt(Instruction *inst) {
   GenIntrinsicInst *intrinCall = llvm::cast<GenIntrinsicInst>(inst);
   CVariable *src0 = GetSymbol(intrinCall->getArgOperand(0));

IGC/Compiler/CISACodeGen/EmitVISAPass.hpp

@@ -439,6 +439,7 @@ class EmitPass : public llvm::FunctionPass {
                       uint32_t SrcSubRegOffset = 0, bool allowLargerSIMDSize = false, CVariable *predicate = nullptr);
   void emitConstantVector(CVariable *Dst, uint64_t value = 0);
   void emitCopyAll(CVariable *Dst, CVariable *Src, llvm::Type *Ty);
+  void emitCopyAllInstances(CVariable *Dst, CVariable *Src, llvm::Type *Ty);
 
   void emitPredicatedVectorCopy(CVariable *Dst, CVariable *Src, CVariable *pred);
   void emitPredicatedVectorSelect(CVariable *Dst, CVariable *Src0, CVariable *Src1, CVariable *pred);

IGC/ocloc_tests/features/reqd_sub_group_size/subroutine.cl

@@ -0,0 +1,44 @@
+/*========================== begin_copyright_notice ============================
+
+Copyright (C) 2025 Intel Corporation
+
+SPDX-License-Identifier: MIT
+
+============================= end_copyright_notice ===========================*/
+
+// REQUIRES: dg2-supported
+// RUN: ocloc compile -file %s -options "-igc_opts 'DumpVISAASMToConsole=1'" -device dg2 | FileCheck --check-prefix CHECK-VISA %s
+
+// This test verifies that function calls as subroutines are properly handled when
+// intel_reqd_sub_group_size is equal to 32 on DG2. The final call instruction must be
+// in the SIMD width required by the user (32), but instructions that are responsible
+// for passing parameters to the subroutine and returning values from the subroutine
+// must be split into two SIMD16 instructions.
+
+// CHECK-VISA: mov (M1, 16) [[A_PARAM_LO:.*]](0,0)<1> {{.*}}(0,0)<0;1,0>
+// CHECK-VISA: mov (M5, 16) [[A_PARAM_HI:.*]](0,0)<1> {{.*}}(0,0)<0;1,0>
+// CHECK-VISA: mov (M1, 16) [[B_PARAM_LO:.*]](0,0)<1> {{.*}}(0,0)<0;1,0>
+// CHECK-VISA: mov (M5, 16) [[B_PARAM_HI:.*]](0,0)<1> {{.*}}(0,0)<0;1,0>
+// CHECK-VISA: call (M1, 32) compute_sum_1
+// CHECK-VISA: mov (M1, 16) {{.*}}(0,0)<1> [[COMPUTE_SUM_RETVAL_LO:.*]](0,0)<1;1,0>
+// CHECK-VISA: mov (M5, 16) {{.*}}(0,0)<1> [[COMPUTE_SUM_RETVAL_HI:.*]](0,0)<1;1,0>
+
+// CHECK-VISA: .function "compute_sum_1"
+// CHECK-VISA: compute_sum_1:
+// CHECK-VISA: add (M1, 16) [[RESULT_LO:.*]](0,0)<1> [[A_PARAM_LO]](0,0)<1;1,0> [[B_PARAM_LO]](0,0)<1;1,0>
+// CHECK-VISA: add (M5, 16) [[RESULT_HI:.*]](0,0)<1> [[A_PARAM_HI]](0,0)<1;1,0> [[B_PARAM_HI]](0,0)<1;1,0>
+// CHECK-VISA: mov (M1, 16) [[COMPUTE_SUM_RETVAL_LO]](0,0)<1> [[RESULT_LO]](0,0)<1;1,0>
+// CHECK-VISA: mov (M5, 16) [[COMPUTE_SUM_RETVAL_HI]](0,0)<1> [[RESULT_HI]](0,0)<1;1,0>
+
+__attribute__((noinline))
+int compute_sum(int a, int b)
+{
+    return a + b;
+}
+
+__attribute__((intel_reqd_sub_group_size(32)))
+kernel void test_sum(global int* out, int x, int y)
+{
+    int result = compute_sum(x, y);
+    out[0] = result;
+}