GEPLSR: disable any int bit width by default

Disable support for any integer bit width in GEPLSR pass.

Author: pkwasnie-intel

IGC/Compiler/Optimizer/OpenCLPasses/GEPLoopStrengthReduction/GEPLoopStrengthReduction.cpp

@@ -1438,15 +1438,16 @@ bool SCEVHelper::isValid(const SCEV *S)
         if (!Ty->isIntegerTy())
             return false;
 
-        switch (Ty->getScalarSizeInBits())
+        auto bits = Ty->getScalarSizeInBits();
+        switch (bits)
         {
         case 8:
         case 16:
         case 32:
         case 64:
             return false;
         default:
-            return true;
+            return bits > 8;
         }
     };
 

IGC/Compiler/tests/GEPLoopStrengthReduction/illegal_types-typed-pointers.ll

@@ -7,8 +7,8 @@
 ;============================ end_copyright_notice =============================
 
 ; REQUIRES: regkeys
-; RUN: igc_opt --regkey=EnableGEPLSRMulExpr=1 --regkey=EnableGEPLSRAnyIntBitWidth=0 -debugify --igc-gep-loop-strength-reduction -check-debugify -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-BLOCK-ILLEGAL
-; RUN: igc_opt --regkey=EnableGEPLSRMulExpr=1 --regkey=EnableGEPLSRAnyIntBitWidth=1 -debugify --igc-gep-loop-strength-reduction -check-debugify -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ALLOW-ILLEGAL
+; RUN: igc_opt --regkey=EnableGEPLSRMulExpr=1 --regkey=EnableGEPLSRAnyIntBitWidth=0 -debugify --igc-gep-loop-strength-reduction -check-debugify -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-BLOCK-ILLEGAL
+; RUN: igc_opt --regkey=EnableGEPLSRMulExpr=1 --regkey=EnableGEPLSRAnyIntBitWidth=1 -debugify --igc-gep-loop-strength-reduction -check-debugify -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-ALLOW-ILLEGAL
 ;
 ; Test for illegal types in SCEV expressions.
 
@@ -75,40 +75,29 @@ for.end:                                          ; preds = %for.cond.for.end_cr
 
 ; Instruction "and" creates SCEV with i7 type:
 ;  (zext i7 {(trunc i64 %b to i7),+,(trunc i64 %a to i7)}<%for.body> to i64)
+; Types <= i8 are correctly legalized.
 define spir_kernel void @test_and(i32 addrspace(1)* %p, i64 %n, i64 %a, i64 %b)  {
 entry:
   %cmp1 = icmp slt i64 0, %n
   br i1 %cmp1, label %for.body.lr.ph, label %for.end
 
-; CHECK-BLOCK-ILLEGAL-LABEL: for.body.lr.ph:
-; CHECK-BLOCK-ILLEGAL:         br label %for.body
-; CHECK-ALLOW-ILLEGAL-LABEL: for.body.lr.ph:
-; CHECK-ALLOW-ILLEGAL:         [[TRUNC1:%.*]] = trunc i64 %b to i7
-; CHECK-ALLOW-ILLEGAL:         [[INDEX:%.*]] = zext i7 [[TRUNC1]] to i64
-; CHECK-ALLOW-ILLEGAL:         [[GEP_PHI1:%.*]] = getelementptr i32, i32 addrspace(1)* %p, i64 [[INDEX]]
-; CHECK-ALLOW-ILLEGAL:         [[TRUNC2:%.*]] = trunc i64 %a to i7
-; CHECK-ALLOW-ILLEGAL:         br label %for.body
+; CHECK-LABEL:               for.body.lr.ph:
+; CHECK:                       [[TRUNC1:%.*]] = trunc i64 %b to i7
+; CHECK:                       [[INDEX:%.*]] = zext i7 [[TRUNC1]] to i64
+; CHECK:                       [[GEP_PHI1:%.*]] = getelementptr i32, i32 addrspace(1)* %p, i64 [[INDEX]]
+; CHECK:                       [[TRUNC2:%.*]] = trunc i64 %a to i7
+; CHECK:                       br label %for.body
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body
 
-; CHECK-BLOCK-ILLEGAL-LABEL: for.body:
-; CHECK-BLOCK-ILLEGAL:         %i.02 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
-; CHECK-BLOCK-ILLEGAL:         %0 = mul i64 %i.02, %a
-; CHECK-BLOCK-ILLEGAL:         %1 = add i64 %0, %b
-; CHECK-BLOCK-ILLEGAL:         %idxprom = and i64 %1, 127
-; CHECK-BLOCK-ILLEGAL:         %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 %idxprom
-; CHECK-BLOCK-ILLEGAL:         store i32 39, i32 addrspace(1)* %arrayidx, align 4
-; CHECK-BLOCK-ILLEGAL:         %inc = add nuw nsw i64 %i.02, 1
-; CHECK-BLOCK-ILLEGAL:         %cmp = icmp slt i64 %inc, %n
-; CHECK-BLOCK-ILLEGAL:         br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge
-; CHECK-ALLOW-ILLEGAL-LABEL: for.body:
-; CHECK-ALLOW-ILLEGAL:         [[GEP:%.*]] = phi i32 addrspace(1)* [ [[GEP_PHI1]], %for.body.lr.ph ], [ [[GEP_PHI2:%.*]], %for.body ]
-; CHECK-ALLOW-ILLEGAL:         %i.02 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
-; CHECK-ALLOW-ILLEGAL:         store i32 39, i32 addrspace(1)* [[GEP]], align 4
-; CHECK-ALLOW-ILLEGAL:         %inc = add nuw nsw i64 %i.02, 1
-; CHECK-ALLOW-ILLEGAL:         %cmp = icmp slt i64 %inc, %n
-; CHECK-ALLOW-ILLEGAL:         [[GEP_PHI2]] = getelementptr i32, i32 addrspace(1)* [[GEP]], i7 [[TRUNC2]]
-; CHECK-ALLOW-ILLEGAL:         br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge
+; CHECK-LABEL:               for.body:
+; CHECK:                       [[GEP:%.*]] = phi i32 addrspace(1)* [ [[GEP_PHI1]], %for.body.lr.ph ], [ [[GEP_PHI2:%.*]], %for.body ]
+; CHECK:                       %i.02 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+; CHECK:                       store i32 39, i32 addrspace(1)* [[GEP]], align 4
+; CHECK:                       %inc = add nuw nsw i64 %i.02, 1
+; CHECK:                       %cmp = icmp slt i64 %inc, %n
+; CHECK:                       [[GEP_PHI2]] = getelementptr i32, i32 addrspace(1)* [[GEP]], i7 [[TRUNC2]]
+; CHECK:                       br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.02 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %0 = mul i64 %i.02, %a

IGC/common/igc_flags.h

@@ -313,7 +313,7 @@ DECLARE_IGC_REGKEY(bool, EnableGEPLSR, true, "Enables GEP Loop Strength Reductio
 DECLARE_IGC_REGKEY(bool, RunGEPLSRAfterLICM, false, "Runs GEP Loop Strength Reduction pass after first LICM", true)
 DECLARE_IGC_REGKEY(DWORD, GEPLSRThresholdRatio, 100, "Ratio for register pressure threshold in GEP Loop Strength Reduction pass", true)
 DECLARE_IGC_REGKEY(bool, EnableGEPLSRToPreheader, true, "Enables reduction to loop's preheader in GEP Loop Strength Reduction pass", true)
-DECLARE_IGC_REGKEY(bool, EnableGEPLSRAnyIntBitWidth, true, "Enables reduction of SCEV with illegal integers. Requires legalization pass to clear up expanded code.", true)
+DECLARE_IGC_REGKEY(bool, EnableGEPLSRAnyIntBitWidth, false, "Enables reduction of SCEV with illegal integers. Requires legalization pass to clear up expanded code.", true)
 DECLARE_IGC_REGKEY(bool, EnableGEPLSRMulExpr, true, "Experimental: Enables reduction of SCEV with mul expression.", true)
 DECLARE_IGC_REGKEY(bool, EnableGEPLSRUnknownConstantStep, false, "Experimental: Enables reduction of SCEV with step expressed with constant value unknown at compilation time.", true)
 DECLARE_IGC_REGKEY(bool, PrintWaveClusteredInterleave, false, "(Debug) Print if WaveClusteredInterleave pattern was found.", true)