Expand MathExtras wrapper

amielcza · igcbot · commit b42e4d2bed01 · 2025-11-25T09:18:57.000+01:00
Expand the MathExtras wrapper to cover methods removed in LLVM17.
diff --git a/IGC/Compiler/CISACodeGen/EmitVISAPass.cpp b/IGC/Compiler/CISACodeGen/EmitVISAPass.cpp
@@ -36,6 +36,7 @@ SPDX-License-Identifier: MIT
 #include "llvmWrapper/IR/Instructions.h"
 #include "llvmWrapper/IR/DerivedTypes.h"
 #include "llvmWrapper/IR/Function.h"
+#include "llvmWrapper/Support/MathExtras.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/FormattedStream.h"
@@ -2587,7 +2588,7 @@ void EmitPass::emitMayUnalignedVectorCopy(CVariable *Dst, uint32_t Dst_off, CVar
       // This alignment must be aligned for both Dst and Src. The max align
       // starts with element size (tyBytes) and decreases.
       uint32_t remainingBytes = eltBytes - off;
-      uint32_t maxAlign = (uint32_t)PowerOf2Floor(remainingBytes);
+      uint32_t maxAlign = (uint32_t)IGCLLVM::bit_floor(remainingBytes);
       uint32_t currAlign = (uint32_t)MinAlign(maxAlign, doff);
       currAlign = (uint32_t)MinAlign(currAlign, soff);
 
@@ -18848,7 +18849,7 @@ void EmitPass::emitUniformVectorCopy(CVariable *Dst, CVariable *Src, uint32_t nE
   // Start with the max execution size that is legal for the vector element
   // and is no greater than the current simdsize.
   uint32_t maxNumElts = (2 * getGRFSize()) / Dst->GetElemSize();
-  uint32_t maxSimd = std::min(width, (uint32_t)PowerOf2Floor(maxNumElts));
+  uint32_t maxSimd = std::min(width, (uint32_t)IGCLLVM::bit_floor(maxNumElts));
   if (maxSimd == 32 && allowLargerSIMDSize) {
     while (partialCopy(SIMDMode::SIMD32))
       ;
diff --git a/IGC/Compiler/CISACodeGen/LdShrink.cpp b/IGC/Compiler/CISACodeGen/LdShrink.cpp
@@ -10,7 +10,7 @@ SPDX-License-Identifier: MIT
 #include <llvm/Pass.h>
 #include <llvm/IR/DataLayout.h>
 #include <llvmWrapper/Support/Alignment.h>
-#include <llvm/Support/MathExtras.h>
+#include <llvmWrapper/Support/MathExtras.h>
 #include <llvmWrapper/IR/DerivedTypes.h>
 #include "common/LLVMWarningsPop.hpp"
 #include "Compiler/CISACodeGen/ShaderCodeGen.hpp"
@@ -116,8 +116,8 @@ bool LdShrink::runOnFunction(Function &F) {
         continue;
       if (!isShiftedMask_32(Mask))
         continue;
-      unsigned Offset = llvm::countTrailingZeros(Mask);
-      unsigned Length = llvm::countTrailingZeros((Mask >> Offset) + 1);
+      unsigned Offset = IGCLLVM::countr_zero(Mask);
+      unsigned Length = IGCLLVM::countr_zero((Mask >> Offset) + 1);
       // TODO: So far skip narrow vector.
       if (Length != 1)
         continue;
diff --git a/IGC/Compiler/Optimizer/OpenCLPasses/AlignmentAnalysis/AlignmentAnalysis.cpp b/IGC/Compiler/Optimizer/OpenCLPasses/AlignmentAnalysis/AlignmentAnalysis.cpp
@@ -11,7 +11,7 @@ SPDX-License-Identifier: MIT
 #include "Compiler/CodeGenPublic.h"
 #include "common/LLVMWarningsPush.hpp"
 #include "llvm/IR/InstIterator.h"
-#include "llvm/Support/MathExtras.h"
+#include "llvmWrapper/Support/MathExtras.h"
 #include "llvm/IR/GetElementPtrTypeIterator.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvmWrapper/Support/Alignment.h"
@@ -175,7 +175,7 @@ Align AlignmentAnalysis::getConstantAlignment(uint64_t C) const {
     return Align(Value::MaximumAlignment);
   }
 
-  return std::min(Align(Value::MaximumAlignment), Align(1ULL << llvm::countTrailingZeros(C)));
+  return std::min(Align(Value::MaximumAlignment), Align(1ULL << IGCLLVM::countr_zero(C)));
 }
 
 Align AlignmentAnalysis::getAlignValue(Value *V) const {
diff --git a/IGC/VectorCompiler/include/GenXUtil.h b/IGC/VectorCompiler/include/GenXUtil.h
@@ -27,6 +27,7 @@ SPDX-License-Identifier: MIT
 
 #include "llvmWrapper/IR/DerivedTypes.h"
 #include <llvmWrapper/ADT/Optional.h>
+#include "llvmWrapper/Support/MathExtras.h"
 
 #include "Probe/Assertion.h"
 
@@ -47,7 +48,7 @@ class Bale;
 // Utility function to get the integral log base 2 of an integer, or -1 if
 // the input is not a power of 2.
 inline int exactLog2(unsigned Val) {
-  unsigned CLZ = llvm::countLeadingZeros(Val);
+  unsigned CLZ = IGCLLVM::countl_zero(Val);
   if (CLZ != 32 && 1U << (31 - CLZ) == Val)
     return 31 - CLZ;
   return -1;
@@ -58,7 +59,7 @@ inline int exactLog2(unsigned Val) {
 template <typename T> inline int log2(T Val) {
   if (Val <= 0)
     return -1;
-  unsigned CLZ = llvm::countLeadingZeros<uint32_t>(Val);
+  unsigned CLZ = IGCLLVM::countl_zero<uint32_t>(Val);
   IGC_ASSERT_EXIT(CLZ < 32);
   return 31 - CLZ;
 }
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXAlignmentInfo.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXAlignmentInfo.cpp
@@ -30,7 +30,7 @@ SPDX-License-Identifier: MIT
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/Support/Debug.h"
-
+#include "llvmWrapper/Support/MathExtras.h"
 #include "Probe/Assertion.h"
 
 #define DEBUG_TYPE "GENX_ALIGNMENT_INFO"
@@ -286,7 +286,7 @@ Alignment AlignmentInfo::get(Value *V) {
  * Alignment constructor given literal value
  */
 Alignment::Alignment(unsigned C) {
-  LogAlign = C ? countTrailingZeros(C) : 31;
+  LogAlign = C ? IGCLLVM::countr_zero(C) : 31;
   ExtraBits = 0;
   ConstBits = (C < MaskForUnknown) ? C : MaskForUnknown;
 }
@@ -303,7 +303,7 @@ Alignment Alignment::getAlignmentForConstant(Constant *C) {
     int64_t SVal = CI->getSExtValue();
     // Get least significant bits to count LogAlign
     unsigned LSBBits = SVal & UnsignedAllOnes;
-    A.LogAlign = LSBBits ? countTrailingZeros(LSBBits) : 31;
+    A.LogAlign = LSBBits ? IGCLLVM::countr_zero(LSBBits) : 31;
 
     A.ExtraBits = 0;
     A.ConstBits = MaskForUnknown;
@@ -348,8 +348,8 @@ Alignment Alignment::merge(Alignment Other) const {
   if (MinLogAlign) {
     unsigned DisagreeExtraBits =
         (ExtraBits ^ Other.ExtraBits) & ((1 << MinLogAlign) - 1);
-    MinLogAlign = std::min(
-        MinLogAlign, (unsigned)llvm::countTrailingZeros(DisagreeExtraBits));
+    MinLogAlign = std::min(MinLogAlign,
+                           (unsigned)IGCLLVM::countr_zero(DisagreeExtraBits));
   }
   IGC_ASSERT_EXIT(MinLogAlign < 32);
   return Alignment(MinLogAlign, ExtraBits & ((1 << MinLogAlign) - 1));
@@ -367,7 +367,7 @@ Alignment Alignment::add(Alignment Other) const {
   if (MinLogAlign) {
     ExtraBits2 = (ExtraBits + Other.ExtraBits) & ((1 << MinLogAlign) - 1);
     MinLogAlign =
-        std::min(MinLogAlign, (unsigned)llvm::countTrailingZeros(ExtraBits2));
+        std::min(MinLogAlign, (unsigned)IGCLLVM::countr_zero(ExtraBits2));
   }
   IGC_ASSERT_EXIT(MinLogAlign < 32);
   return Alignment(MinLogAlign, ExtraBits2 & ((1 << MinLogAlign) - 1));
@@ -391,7 +391,7 @@ Alignment Alignment::mul(Alignment Other) const {
   if (MinLogAlign) {
     ExtraBits2 = (ExtraBits * Other.ExtraBits) & ((1 << MinLogAlign) - 1);
     MinLogAlign =
-        std::min(MinLogAlign, (unsigned)llvm::countTrailingZeros(ExtraBits2));
+        std::min(MinLogAlign, (unsigned)IGCLLVM::countr_zero(ExtraBits2));
   }
   IGC_ASSERT_EXIT(MinLogAlign < 32);
   return Alignment(MinLogAlign, ExtraBits2 & ((1 << MinLogAlign) - 1));
@@ -410,7 +410,7 @@ Alignment Alignment::logicalOp(ConstantInt *CI, SelectFunction F) const {
       Val > std::numeric_limits<int>::max())
     return Alignment::getUnknown();
   unsigned UVal = static_cast<unsigned>(std::abs(Val));
-  unsigned ValLSB = llvm::countTrailingZeros(UVal);
+  unsigned ValLSB = IGCLLVM::countr_zero(UVal);
   // Chop off constant bits according to log align
   unsigned NewLogAlign = F(ValLSB, LogAlign);
   IGC_ASSERT_EXIT(NewLogAlign < 32);
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXConstants.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXConstants.cpp
@@ -1301,8 +1301,8 @@ unsigned ConstantLoader::getRegionBits(unsigned NeededBits,
   if (!NeededBits)
     return 0;
   // Get the first and last element numbers in NeededBits.
-  unsigned FirstNeeded = llvm::countTrailingZeros(NeededBits);
-  unsigned LastNeeded = 31 - llvm::countLeadingZeros((uint32_t)NeededBits);
+  unsigned FirstNeeded = IGCLLVM::countr_zero(NeededBits);
+  unsigned LastNeeded = 31 - IGCLLVM::countl_zero((uint32_t)NeededBits);
   // Set the max width to the min size including both those elements
   // rounded up to the next power of two.
   unsigned MaxWidth = LastNeeded - FirstNeeded + 1;
@@ -1503,8 +1503,8 @@ Instruction *ConstantLoader::loadNonPackedIntConst(Instruction *InsertBefore) {
   unsigned NumElements = CTy->getNumElements();
   Instruction *Result = nullptr;
   for (unsigned Idx = 0; Idx != NumElements;) {
-    unsigned Size =
-        std::min(PowerOf2Floor(NumElements - Idx), (uint64_t)ImmIntVec::Width);
+    unsigned Size = std::min(IGCLLVM::bit_floor(NumElements - Idx),
+                             (uint64_t)ImmIntVec::Width);
     Constant *SubC = getConstantSubvector(C, Idx, Size);
     Value *SubV = SubC;
     ConstantLoader SubLoader(SubC, Subtarget, DL);
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXLegalization.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXLegalization.cpp
@@ -1217,8 +1217,7 @@ unsigned GenXLegalization::determineWidth(unsigned WholeWidth,
     ExecSizeAllowedBits &= 0x1f;
 
   IGC_ASSERT_EXIT(ExecSizeAllowedBits > 0);
-  unsigned MainInstMinWidth = 1
-                              << llvm::countTrailingZeros(ExecSizeAllowedBits);
+  unsigned MainInstMinWidth = 1 << IGCLLVM::countr_zero(ExecSizeAllowedBits);
   // Determine the vector width that we need to split into.
   bool IsReadSameVector = false;
   unsigned Width = WholeWidth - StartIdx;
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXLowerAggrCopies.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXLowerAggrCopies.cpp
@@ -35,6 +35,7 @@ SPDX-License-Identifier: MIT
 #include "llvmWrapper/IR/DerivedTypes.h"
 #include "llvmWrapper/IR/Type.h"
 #include "llvmWrapper/Support/Alignment.h"
+#include "llvmWrapper/Support/MathExtras.h"
 
 #include "vc/GenXCodeGen/GenXLowerAggrCopies.h"
 
@@ -98,7 +99,7 @@ struct SliceInfo {
 static std::vector<SliceInfo> getLegalLengths(int TotalLength, int Align) {
   std::vector<SliceInfo> Slices;
   for (int Offset = 0; TotalLength;) {
-    int Width = PowerOf2Floor(TotalLength);
+    int Width = IGCLLVM::bit_floor(TotalLength);
     Slices.push_back({Offset, Width, Align});
 
     Offset += Width;
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp
@@ -119,6 +119,7 @@ SPDX-License-Identifier: MIT
 #include "llvmWrapper/IR/DerivedTypes.h"
 #include "llvmWrapper/IR/Instructions.h"
 #include "llvmWrapper/Support/TypeSize.h"
+#include "llvmWrapper/Support/MathExtras.h"
 
 #include "vc/Support/GenXDiagnostic.h"
 #include "vc/Utils/GenX/GlobalVariable.h"
@@ -4206,8 +4207,9 @@ static LoHiRes buildIMadWithMadw(ArrayRef<Value *> Args, bool Signed,
   LoHiRes Res = {UndefValue::get(OpTy), UndefValue::get(OpTy)};
   unsigned StartIdx = 0;
   while (StartIdx < OpWidth) {
-    unsigned SplitWidth = std::min(
-        TargetWidth, static_cast<unsigned>(PowerOf2Floor(OpWidth - StartIdx)));
+    unsigned SplitWidth =
+        std::min(TargetWidth,
+                 static_cast<unsigned>(IGCLLVM::bit_floor(OpWidth - StartIdx)));
 
     std::array<Value *, 3> SplitArgs;
     for (unsigned i = 0; i < Args.size(); ++i)
@@ -5150,7 +5152,7 @@ bool GenXLowering::lowerReduction(CallInst *CI, Value *Src, Value *Start,
     }
     SrcWidth = LinearGrain;
   } else if (!isPowerOf2_32(SrcWidth)) {
-    TailIndex = PowerOf2Floor(SrcWidth);
+    TailIndex = IGCLLVM::bit_floor(SrcWidth);
     IGC_ASSERT_EXIT(TailIndex);
     TailWidth = SrcWidth % TailIndex;
     SrcWidth = TailIndex;
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXLscAddrCalcFolding.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXLscAddrCalcFolding.cpp
@@ -13,6 +13,7 @@ SPDX-License-Identifier: MIT
 #include "vc/Utils/GenX/IntrinsicsWrapper.h"
 
 #include "llvmWrapper/IR/Instructions.h"
+#include "llvmWrapper/Support/MathExtras.h"
 
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/InstVisitor.h"
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXReduceIntSize.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXReduceIntSize.cpp
@@ -70,6 +70,7 @@ SPDX-License-Identifier: MIT
 
 #include "llvmWrapper/IR/DerivedTypes.h"
 #include "llvmWrapper/IR/Instructions.h"
+#include "llvmWrapper/Support/MathExtras.h"
 
 #define DEBUG_TYPE "GENX_REDUCEINTSIZE"
 
@@ -201,7 +202,7 @@ static unsigned getAndNumBits(Instruction *Inst) {
   if (auto C = dyn_cast<Constant>(Inst->getOperand(1))) {
     if ((C = C->getSplatValue())) {
       uint64_t Val = cast<ConstantInt>(C)->getZExtValue();
-      return 64 - llvm::countLeadingZeros(Val);
+      return 64 - IGCLLVM::countl_zero(Val);
     }
   }
   return Inst->getType()->getScalarType()->getPrimitiveSizeInBits();
@@ -965,7 +966,7 @@ GenXReduceIntSize::getValueNumBits(Value *V, bool PreferSigned) {
     if (C) {
       int64_t Val = cast<ConstantInt>(C)->getSExtValue();
       if (Val >= 0)
-        return ValueNumBits(64 - llvm::countLeadingZeros((uint64_t)Val) +
+        return ValueNumBits(64 - IGCLLVM::countl_zero((uint64_t)Val) +
                                 PreferSigned,
                             /*IsSignExtended=*/PreferSigned);
       if (Val == std::numeric_limits<int64_t>::min())
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXRegionUtils.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXRegionUtils.cpp
@@ -36,6 +36,7 @@ SPDX-License-Identifier: MIT
 
 #include "llvmWrapper/IR/DerivedTypes.h"
 #include "llvmWrapper/Support/TypeSize.h"
+#include "llvmWrapper/Support/MathExtras.h"
 
 using namespace llvm;
 using namespace genx;
@@ -970,7 +971,7 @@ convertRegionInstType(Instruction *Inst, Type *NewScalarTy,
     return std::nullopt;
   // Transformation is not profitable for 2D regions or if it will require
   // legalization.
-  if (R.is2D() || R.NumElements > llvm::PowerOf2Floor(
+  if (R.is2D() || R.NumElements > IGCLLVM::bit_floor(
                                       genx::getExecSizeAllowedBits(Inst, &ST)))
     return std::nullopt;
   return std::make_pair(NewVecTy, R);
diff --git a/IGC/VectorCompiler/lib/GenXOpts/CMTrans/CMABI.cpp b/IGC/VectorCompiler/lib/GenXOpts/CMTrans/CMABI.cpp
@@ -26,6 +26,7 @@ SPDX-License-Identifier: MIT
 #include "llvmWrapper/IR/Function.h"
 #include "llvmWrapper/IR/Instructions.h"
 #include "llvmWrapper/Support/Alignment.h"
+#include "llvmWrapper/Support/MathExtras.h"
 
 #include "Probe/Assertion.h"
 
@@ -994,8 +995,8 @@ void CMABIBase<CallGraphImpl>::diagnoseOverlappingArgs(CallInst *CI) {
                                    ->getScalarType()
                                    ->getPrimitiveSizeInBits();
 
-      int LogRatio = llvm::countTrailingZeros(OutElementSize) -
-                     llvm::countTrailingZeros(InElementSize);
+      int LogRatio = IGCLLVM::countr_zero(OutElementSize) -
+                     IGCLLVM::countr_zero(InElementSize);
 
       auto OpndEntry = &ValMap[BC->getOperand(0)];
       if (!LogRatio)
diff --git a/IGC/VectorCompiler/lib/Utils/GenX/Region.cpp b/IGC/VectorCompiler/lib/Utils/GenX/Region.cpp
@@ -29,7 +29,7 @@ SPDX-License-Identifier: MIT
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/Support/MathExtras.h"
+#include "llvmWrapper/Support/MathExtras.h"
 #include "Probe/Assertion.h"
 
 using namespace llvm;
@@ -214,18 +214,18 @@ CMRegion::CMRegion(unsigned Bits, unsigned ElementBytes)
       Width(1), Stride(1), Offset(0), Indirect(0), IndirectIdx(0),
       IndirectAddrOffset(0), Mask(0), ParentWidth(0) {
   IGC_ASSERT(Bits);
-  Offset = llvm::countTrailingZeros(Bits);
+  Offset = IGCLLVM::countr_zero(Bits);
 
-  // It might seem problematic that countTrailingZeros may return 32 and that we
-  // could do shift by 32 here. But countTrailingZeros would return 32 in
+  // It might seem problematic that countr_zero may return 32 and that we
+  // could do shift by 32 here. But countr_zero would return 32 in
   // scenario where "Bits" variable is 0 And IGC_ASSERT(Bits) covers this
   // case... in debug mode, at least.
   if (Offset < std::numeric_limits<unsigned>::digits) {
     Bits >>= Offset;
     Offset *= ElementBytes;
 
     if (Bits != 1) {
-      Stride = llvm::countTrailingZeros(Bits & ~1);
+      Stride = IGCLLVM::countr_zero(Bits & ~1);
       NumElements = Width = countPopulation(Bits);
     }
   }
diff --git a/IGC/WrapperLLVM/include/llvmWrapper/Support/MathExtras.h b/IGC/WrapperLLVM/include/llvmWrapper/Support/MathExtras.h
@@ -15,6 +15,32 @@ SPDX-License-Identifier: MIT
 namespace IGCLLVM {
 using llvm::MulOverflow;
 using llvm::SubOverflow;
-} // namespace IGCLLVM
 
+inline uint64_t bit_floor(uint64_t A) {
+#if LLVM_VERSION_MAJOR > 16
+  return llvm::bit_floor(A);
+#else
+  return llvm::PowerOf2Floor(A);
+#endif
+}
+
+template <typename T> unsigned countr_zero(T Val) {
+  static_assert(std::is_unsigned_v<T>, "Only unsigned integral types are allowed.");
+#if LLVM_VERSION_MAJOR > 16
+  return llvm::countr_zero(Val);
+#else
+  return llvm::countTrailingZeros(Val);
 #endif
+}
+
+template <typename T> unsigned countl_zero(T Val) {
+  static_assert(std::is_unsigned_v<T>, "Only unsigned integral types are allowed.");
+#if LLVM_VERSION_MAJOR > 16
+  return llvm::countl_zero(Val);
+#else
+  return llvm::countLeadingZeros(Val);
+#endif
+}
+} // namespace IGCLLVM
+
+#endif
