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Remove special pattern handling code from interference building
function Change-Id: Ib03643c720c7938058f67e002bc353c4822c7149
1 parent 0993c06 commit bd548a2

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1 file changed

+3
-136
lines changed

1 file changed

+3
-136
lines changed

visa/GraphColor.cpp

Lines changed: 3 additions & 136 deletions
Original file line numberDiff line numberDiff line change
@@ -1794,143 +1794,10 @@ void Interference::buildInterferenceForDst(G4_BB* bb, BitSet& live, G4_INST* ins
17941794
{
17951795
lrs[id]->setRefCount(lrs[id]->getRefCount() + refCount); // update reference count
17961796

1797-
if (inst->getEvenlySplitInst() && !lrs[id]->getIsSplittedDcl())
1798-
{
1799-
std::list<G4_INST*>::reverse_iterator succ = i;
1800-
succ--;
1801-
G4_INST* nextInst = (*succ);
1802-
G4_DstRegRegion* nextDst = nextInst->getDst();
1803-
1804-
bool needUpdate = false;
1805-
1806-
// Perform addtional sanity checks to make sure
1807-
// - no temp instruction is inserted between the splitted instructions due to other HW conformity fix
1808-
// - no new live range is introduced by (future) value numbering optimization
1809-
1810-
if (inst->opcode() != nextInst->opcode() ||
1811-
inst->getExecSize() != inst->getExecSize())
1812-
{
1813-
needUpdate = true;
1814-
}
1815-
1816-
if (needUpdate == false &&
1817-
nextDst != NULL &&
1818-
nextDst->getBase()->isRegAllocPartaker() &&
1819-
(dst->getBase()->asRegVar()->getId() !=
1820-
nextDst->getBase()->asRegVar()->getId()))
1821-
{
1822-
needUpdate = true;
1823-
}
1824-
1825-
if (needUpdate == false)
1826-
{
1827-
for (unsigned j = 0; j < G4_MAX_SRCS; j++)
1828-
{
1829-
G4_Operand* src = inst->getSrc(j);
1830-
G4_Operand* nextSrc = nextInst->getSrc(j);
1831-
if (src != NULL &&
1832-
src->isSrcRegRegion() &&
1833-
src->asSrcRegRegion()->getBase()->isRegAllocPartaker() &&
1834-
nextSrc != NULL &&
1835-
nextSrc->isSrcRegRegion() &&
1836-
nextSrc->asSrcRegRegion()->getBase()->isRegAllocPartaker() &&
1837-
(src->asSrcRegRegion()->getBase()->asRegVar()->getId() !=
1838-
nextSrc->asSrcRegRegion()->getBase()->asRegVar()->getId()))
1839-
{
1840-
needUpdate = true;
1841-
}
1842-
}
1843-
}
1844-
1845-
if (needUpdate)
1846-
{
1847-
buildInterferenceWithLive(live, id);
1848-
1849-
if (lrs[id]->getIsSplittedDcl())
1850-
{
1851-
buildInterferenceWithSubDcl(id, (G4_Operand *)dst, live, false, true);
1852-
}
1853-
}
1854-
else
1855-
{
1856-
if (!(builder.getOption(vISA_LocalRA) && !gra.isReRAPass()))
1857-
{
1858-
G4_Declare* decl = dst->getBase()->asRegVar()->getDeclare()->getRootDeclare();
1859-
decl->setAlign(Even);
1860-
}
1861-
1862-
for (unsigned j = 0; j < G4_MAX_SRCS; j++)
1863-
{
1864-
G4_Operand* src = inst->getSrc(j);
1865-
G4_Operand* nextSrc = nextInst->getSrc(j);
1866-
unsigned int srcRightBound = 0;
1867-
unsigned int nextSrcLeftBound = 0;
1868-
1869-
if (src != NULL &&
1870-
src->isSrcRegRegion() &&
1871-
src->asSrcRegRegion()->getBase()->isRegAllocPartaker() &&
1872-
nextSrc != NULL &&
1873-
nextSrc->isSrcRegRegion() &&
1874-
nextSrc->asSrcRegRegion()->getBase()->isRegAllocPartaker())
1875-
{
1876-
bool interferenceSet = false;
1877-
1878-
if (dst->getBase()->isRegAllocPartaker() &&
1879-
nextDst != NULL &&
1880-
nextDst->getBase()->isRegAllocPartaker())
1881-
{
1882-
unsigned int dstRightBound = 0;
1883-
unsigned int nextDstLeftBound = 0;
1884-
1885-
dstRightBound = dst->getRightBound();
1886-
nextDstLeftBound = nextDst->getLeftBound();
1887-
1888-
if (dstRightBound / GENX_GRF_REG_SIZ == nextDstLeftBound / GENX_GRF_REG_SIZ)
1889-
{
1890-
interferenceSet = true;
1891-
if (!varSplitCheckBeforeIntf(dst->getBase()->asRegVar()->getId(),
1892-
src->asSrcRegRegion()->getBase()->asRegVar()->getId()))
1893-
{
1894-
checkAndSetIntf(dst->getBase()->asRegVar()->getId(),
1895-
src->asSrcRegRegion()->getBase()->asRegVar()->getId());
1896-
}
1897-
1898-
}
1899-
}
1900-
1901-
if (interferenceSet == false)
1902-
{
1903-
srcRightBound = src->getRightBound();
1904-
nextSrcLeftBound = nextSrc->getLeftBound();
1905-
1906-
if (srcRightBound / GENX_GRF_REG_SIZ == nextSrcLeftBound / GENX_GRF_REG_SIZ)
1907-
{
1908-
if (!varSplitCheckBeforeIntf(dst->getBase()->asRegVar()->getId(),
1909-
src->asSrcRegRegion()->getBase()->asRegVar()->getId()))
1910-
{
1911-
checkAndSetIntf(dst->getBase()->asRegVar()->getId(),
1912-
src->asSrcRegRegion()->getBase()->asRegVar()->getId());
1913-
}
1914-
}
1915-
}
1916-
1917-
1918-
if (!(builder.getOption(vISA_LocalRA) && !gra.isReRAPass()))
1919-
{
1920-
G4_Declare* decl = src->asSrcRegRegion()->getBase()->asRegVar()->getDeclare()->getRootDeclare();
1921-
decl->setAlign(Even);
1922-
}
1923-
}
1924-
}
1925-
}
1926-
}
1927-
else
1797+
buildInterferenceWithLive(live, id);
1798+
if (lrs[id]->getIsSplittedDcl())
19281799
{
1929-
buildInterferenceWithLive(live, id);
1930-
if (lrs[id]->getIsSplittedDcl())
1931-
{
1932-
buildInterferenceWithSubDcl(id, (G4_Operand *)dst, live, false, true);
1933-
}
1800+
buildInterferenceWithSubDcl(id, (G4_Operand *)dst, live, false, true);
19341801
}
19351802
}
19361803

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