Synchronization change between internal branches.

Change-Id: I7acf64fe55a03c5d26300383168774de9c66f66e

Author: pszymich

visa/FlowGraph.cpp

@@ -2968,14 +2968,14 @@ void FlowGraph::processGoto(bool HasSIMDCF)
             if (activeJoinBlocks.size() > 1 ||
                 (activeJoinBlocks.size() == 1 && activeJoinBlocks.back().IsNestedJoin))
             {
-                bb->setInNestedDivergentBranch(true);
+                setInNestedDivergentBranch(bb);
             }
         }
         else if ((builder->getuint32Option(vISA_noMaskToAnyhWA) & 0x3) > 0)
         {
             if (activeJoinBlocks.size() > 0)
             {
-                bb->setInNestedDivergentBranch(true);
+                setInNestedDivergentBranch(bb);
             }
         }
 

visa/FlowGraph.h

@@ -284,21 +284,6 @@ class G4_BB
     // if the block is under simd flow control
     bool inSimdFlow;
 
-    // [HW WA]
-    // If the block does not post-dominate the entry, it is considered
-    // as divergent BB. Within a divergent BB, a further divergence is
-    // considered as nested divergent.
-    //
-    // [Formal def] define root_1_divergentBB (level 1 divergent root)
-    // to be BBs that
-    //     1.  not pdom(BB, entry); and
-    //     2.  There exists P, so that idom(P, BB) && pdom(P, entry)
-    // A BB is in a nested divergent branch if  there is a root_1_divergentBB,
-    // say B1,  such that dom(B1, BB) && not pdom(BB, B1).
-    //
-    // This is set in processGoto().
-    bool inNestedDivergentBranch;
-
     // the physical pred/succ for this block (i.e., the pred/succ for this block in the BB list)
     // Note that some transformations may rearrange BB layout, so for safety it's best to recompute
     // this
@@ -384,8 +369,7 @@ class G4_BB
         traversal(0), idom(NULL), beforeCall(NULL),
         afterCall(NULL), calleeInfo(NULL), BBType(G4_BB_NONE_TYPE),
         inNaturalLoop(false), hasSendInBB(false), loopNestLevel(0), scopeID(0),
-        inSimdFlow(false), inNestedDivergentBranch(false),
-        physicalPred(NULL), physicalSucc(NULL), parent(fg),
+        inSimdFlow(false), physicalPred(NULL), physicalSucc(NULL), parent(fg),
         instList(alloc)
     {
     }
@@ -430,10 +414,6 @@ class G4_BB
 
     void     setSendInBB(bool val)        { hasSendInBB = val; }
     bool     isSendInBB()                { return hasSendInBB; }
-
-    void     setInNestedDivergentBranch(bool val) { inNestedDivergentBranch = val; }
-    bool     isInNestedDivergentBranch() const    { return inNestedDivergentBranch; }
-
     void     setNestLevel()                   {loopNestLevel ++;}
     unsigned char getNestLevel()              {return loopNestLevel;}
     void     resetNestLevel()                 { loopNestLevel = 0; }
@@ -706,6 +686,21 @@ class FlowGraph
     // ToDo: We should use FuncInfo instead, but at the time it was needed FuncInfo was not constructed yet..
     std::unordered_map<G4_Label*, std::vector<G4_BB*>> subroutines;
 
+    // [HW WA]
+    // If the block does not post-dominate the entry, it is considered
+    // as divergent BB. Within a divergent BB, a further divergence is
+    // considered as nested divergent.
+    //
+    // [Formal def] define root_1_divergentBB (level 1 divergent root)
+    // to be BBs that
+    //     1.  not pdom(BB, entry); and
+    //     2.  There exists P, so that idom(P, BB) && pdom(P, entry)
+    // A BB is in a nested divergent branch if  there is a root_1_divergentBB,
+    // say B1,  such that dom(B1, BB) && not pdom(BB, B1).
+    //
+    // This is set in processGoto().
+    std::unordered_map<G4_BB*, int> nestedDivergentBBs;
+
 public:
     typedef std::pair<G4_BB*, G4_BB*> Edge;
     typedef std::set<G4_BB*> Blocks;
@@ -922,6 +917,15 @@ class FlowGraph
         return false;
     }
 
+    void setInNestedDivergentBranch(G4_BB* B)
+    {
+        nestedDivergentBBs[B] = 1;
+    }
+    bool isInNestedDivergentBranch(G4_BB* B) const
+    {
+        return nestedDivergentBBs.count(B) > 0;
+    }
+
     //
     // Merge multiple returns into one, prepare for spill code insertion
     //

visa/Gen4_IR.cpp

@@ -3312,16 +3312,22 @@ G4_INST::isComprInvariantSrcRegion(G4_SrcRegRegion* src, int srcPos)
 bool G4_INST::isPartialWrite() const
 {
     G4_Predicate* aPred = predicate;
-    if (aPred && G4_Predicate::isAnyH(aPred->getControl()) &&
-        builder.kernel.getOptions()->getTarget() != VISA_CM)
+    if (builder.kernel.getOptions()->getTarget() != VISA_CM &&
+        (builder.getuint32Option(vISA_noMaskToAnyhWA) & 0x3) > 0 &&
+        (getGenxPlatform() == GENX_TGLLP ||
+            builder.getOption(vISA_forceNoMaskToAnyhWA)))
     {
         // Only for code from IGC. HW WA related.
-        if (aPred->getPredCtrlGroupSize() >= builder.kernel.getSimdSize())
+        if (aPred && G4_Predicate::isAnyH(aPred->getControl()))
         {
-            // This is equivalent to NoMask
-            aPred = nullptr;
+            if (aPred->getPredCtrlGroupSize() >= builder.kernel.getSimdSize())
+            {
+                // equivalent to NoMask without predicate [ie (w)]
+                aPred = nullptr;
+            }
         }
     }
+
     return (aPred != NULL && op != G4_sel) || op == G4_smov;
 }
 

visa/Optimizer.cpp

@@ -11747,7 +11747,7 @@ void Optimizer::replaceNoMaskWithAnyhWA()
     for (auto BI : fg)
     {
         G4_BB* BB = BI;
-        if (!BB->isInNestedDivergentBranch()) {
+        if (fg.isInNestedDivergentBranch(BB)) {
             continue;
         }
 
@@ -11808,7 +11808,7 @@ void Optimizer::replaceNoMaskWithAnyhWA()
         //                         (2) (W) mov (1|M0) f1.0<1>:ud  ce0.0<0;1,0>:ud
         //                             (f1.0.any16h)  inst1
         // The algo tries to use (1) if doing so has lower chance to increase flag
-        // register pressure; otherwise, it uses (2).
+        // register pressure and if f0.0 is local; otherwise, it uses (2).
 
         // 1. Check if an existing flag can be used
         //    If BB's predecessor ends with a conditional goto instruction,
@@ -11822,7 +11822,9 @@ void Optimizer::replaceNoMaskWithAnyhWA()
             assert(gotoInst->opcode() == G4_goto && "Last inst should be goto!");
             G4_Predicate* pred = gotoInst->getPredicate();
             if (predBB->Succs.size() == 2 &&
-                pred && pred->getControl() == PRED_DEFAULT) {
+                pred && pred->getControl() == PRED_DEFAULT &&
+                !fg.globalOpndHT.isOpndGlobal(pred))
+            {
                 prevPred = pred;
                 predTargetBB = predBB->Succs.back();
             }
@@ -11868,12 +11870,9 @@ void Optimizer::replaceNoMaskWithAnyhWA()
             assert(predTargetBB && "predTargetBB should not be null here");
 
             // First, make Pred global
-            if (!fg.globalOpndHT.isOpndGlobal(prevPred))
-            {
-                fg.globalOpndHT.addGlobalOpnd(prevPred);
-            }
-            flagVarForBB = prevPred->getBase()->asRegVar();
+            fg.globalOpndHT.addGlobalOpnd(prevPred);
 
+            flagVarForBB = prevPred->getBase()->asRegVar();
             if ((predTargetBB == BB && prevPred->getState() == PredState_Minus) ||
                 (predTargetBB != BB && prevPred->getState() == PredState_Plus))
             {