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Add LIT Tests for ConstantCoalescing Alignment Checks
Adds new LIT tests to validate the functionality of the ConstantCoalescing::MergeUniformLoad function, specifically focusing on alignment checks.
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‎IGC/Compiler/tests/ConstantCoalescing/ldraws-alignment.ll‎

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2022-2024 Intel Corporation
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; Copyright (C) 2022-2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; RUN: igc_opt --opaque-pointers %s -S -o - -igc-constant-coalescing -instcombine -dce | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f80:128:128-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a:64:64-f80:128:128-n8:16:32:64"
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; Test Case 1: Basic Test Case with Power-of-2 Alignment
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define <4 x half> @f0(i32 %src) {
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entry:
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%bso = inttoptr i32 %src to ptr addrspace(2490373)
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; CHECK: [[RET:%.*]] = call <4 x half> @llvm.genx.GenISA.ldrawvector.indexed.v4f16.p2490373(ptr addrspace(2490373) [[BSO]], i32 [[OFF]], i32 4, i1 false)
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; CHECK: ret <4 x half> [[RET]]
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; Test Case 2: Non-Power-of-2 Alignment
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define <4 x half> @f1(i32 %src) {
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entry:
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%bso = inttoptr i32 %src to ptr addrspace(2490373)
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%ox = shl i32 %src, 2
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%x = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373) %bso, i32 %ox, i32 7, i1 false)
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%oy = add i32 %ox, 2
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%y = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373) %bso, i32 %oy, i32 7, i1 false)
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%oz = add i32 %ox, 4
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%z = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373) %bso, i32 %oz, i32 7, i1 false)
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%ow = add i32 %ox, 6
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%w = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373) %bso, i32 %ow, i32 7, i1 false)
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%ret.x = insertelement <4 x half> undef, half %x, i32 0
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%ret.xy = insertelement <4 x half> %ret.x, half %y, i32 1
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%ret.xyz = insertelement <4 x half> %ret.xy, half %z, i32 2
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%ret.xyzw = insertelement <4 x half> %ret.xyz, half %w, i32 3
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ret <4 x half> %ret.xyzw
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}
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; CHECK-LABEL: define <4 x half> @f1
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; CHECK-NOT: call <4 x half> @llvm.genx.GenISA.ldrawvector.indexed.v4f16.p2490373
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; Test Case 3: Offset Not a Multiple of Scalar Size
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define <4 x half> @f2(i32 %src) {
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entry:
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%bso = inttoptr i32 %src to ptr addrspace(2490373)
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%ox = shl i32 %src, 3
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%x = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373) %bso, i32 %ox, i32 2, i1 false)
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%oy = add i32 %ox, 3
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%y = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373) %bso, i32 %oy, i32 2, i1 false)
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%oz = add i32 %ox, 5
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%z = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373) %bso, i32 %oz, i32 2, i1 false)
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%ow = add i32 %ox, 7
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%w = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373) %bso, i32 %ow, i32 2, i1 false)
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%ret.x = insertelement <4 x half> undef, half %x, i32 0
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%ret.xy = insertelement <4 x half> %ret.x, half %y, i32 1
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%ret.xyz = insertelement <4 x half> %ret.xy, half %z, i32 2
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%ret.xyzw = insertelement <4 x half> %ret.xyz, half %w, i32 3
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ret <4 x half> %ret.xyzw
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}
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; CHECK-LABEL: define <4 x half> @f2
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; CHECK-NOT: call <4 x half> @llvm.genx.GenISA.ldrawvector.indexed.v4f16.p249037
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; Function Attrs: argmemonly nounwind readonly
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declare float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(ptr addrspace(2490373), i32, i32, i1) #0
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; Function Attrs: argmemonly nounwind readonly
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declare float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(ptr addrspace(2490373), i32, i32, i1) argmemonly nounwind readonly
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declare half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373), i32, i32, i1) argmemonly nounwind readonly
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declare half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373i8(ptr addrspace(2490373), i32, i32, i1) #0
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; Function Attrs: argmemonly nounwind writeonly
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declare void @llvm.genx.GenISA.storeraw.indexed.p2490368i8.f32(ptr addrspace(2490373), i32, float, i32, i1) argmemonly nounwind writeonly
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declare void @llvm.genx.GenISA.storeraw.indexed.p2490368i8.f32(ptr addrspace(2490373), i32, float, i32, i1) #1
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; Function Attrs: argmemonly nounwind readonly willreturn
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declare <1 x half> @llvm.genx.GenISA.ldrawvector.indexed.v1f16.p2490373(ptr addrspace(2490373), i32, i32, i1) #2
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; Function Attrs: argmemonly nounwind readonly willreturn
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declare <2 x half> @llvm.genx.GenISA.ldrawvector.indexed.v2f16.p2490373(ptr addrspace(2490373), i32, i32, i1) #2
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!igc.functions = !{!0}
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; Function Attrs: argmemonly nounwind readonly willreturn
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declare <4 x half> @llvm.genx.GenISA.ldrawvector.indexed.v4f16.p2490373(ptr addrspace(2490373), i32, i32, i1) #2
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!0 = !{<4 x half> (i32)* @f0, !1}
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attributes #0 = { argmemonly nounwind readonly }
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attributes #1 = { argmemonly nounwind writeonly }
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attributes #2 = { argmemonly nounwind readonly willreturn }
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!igc.functions = !{!0, !3, !6}
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!0 = !{ptr @f0, !1}
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!1 = !{!2}
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!2 = !{!"function_type", i32 0}
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!3 = !{ptr @f1, !4}
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!4 = !{!5}
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!5 = !{!"function_type", i32 0}
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!6 = !{ptr @f2, !7}
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!7 = !{!8}
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!8 = !{!"function_type", i32 0}

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