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Commit d579932

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bcheng0127igcbot
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Retry bundle based RA assignment
When there is bundle requirement, register assign may fail.
1 parent 3fb00d1 commit d579932

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2 files changed

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-0
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2 files changed

+7
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visa/GraphColor.cpp

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Original file line numberDiff line numberDiff line change
@@ -1051,6 +1051,7 @@ void BankConflictPass::setupBankConflictsForBBTGL(G4_BB *bb,
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if (inst->getNumSrc() >= 3) {
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threeSourceInstNum++;
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if (inst->isDpas()) {
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threeSourceInstNum += 8;
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hasDpasInst = true;
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setupBankConflictsforDPAS(inst);
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} else {

visa/PhyRegUsage.cpp

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Original file line numberDiff line numberDiff line change
@@ -975,6 +975,12 @@ bool PhyRegUsage::assignRegs(bool highInternalConflict, LiveRange *varBasis,
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FPR.availableGregs, forbidden, occupiedBundles,
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getAlignToUse(align, bankAlign), decl->getNumRows(), endGRFReg,
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AS.startGRFReg, i, forceCalleeSaveAlloc, varBasis->getEOTSrc());
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if (!success && occupiedBundles) {
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success = findContiguousGRF(
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FPR.availableGregs, forbidden, 0,
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getAlignToUse(align, bankAlign), decl->getNumRows(), endGRFReg,
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AS.startGRFReg, i, forceCalleeSaveAlloc, varBasis->getEOTSrc());
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}
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if (success) {
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varBasis->setPhyReg(regPool.getGreg(i), 0);
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}

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