Add internal uus_add instruction

.

Author: igorban-intel

IGC/VectorCompiler/include/vc/InternalIntrinsics/Intrinsic_definitions.py

@@ -226,6 +226,23 @@
                       "memory_effects":
                         { "access": "ModRef" }, },
 
+## ``llvm.vc.internal.add.uus.sat`` : add instruction with saturation
+## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+##
+## * arg0: first input, any scalar/vector integer type, even i64 : unsigned
+## * arg1: second input, same type as arg0 : signed
+##
+## * Return value: result of addition, same type as arg0 : unsigned, saturated
+##
+## This intrinsic is used to implement the addition of unsigned and signed
+## integers with saturation.
+##
+    "add_uus_sat" : { "result": "anyint",
+                      "arguments": [ 0, 0 ],
+                      "attributes": "None",
+                      "memory_effects":
+                        { "access": "ModRef" }, },
+
 ## ``llvm.vc.internal.rsqrtm`` : computes component-wise reciprocal square root
 ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 ##

IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp

@@ -3495,14 +3495,30 @@ bool GenXLowering::lowerUAddWithSat(CallInst *CI) {
   return true;
 }
 
+// common subroutine for sub+sat: builds uadd (uus) with sat
+static CallInst *buildUUSAddWithSat(CallInst *CI, Value *Arg0, Value *Arg1,
+                                    Instruction *InsertPoint) {
+  IGC_ASSERT(CI);
+  const DebugLoc &DL = CI->getDebugLoc();
+  Module *M = CI->getModule();
+  IRBuilder<> Builder(InsertPoint);
+  Type *ArgTypes[] = {Arg0->getType(), Arg1->getType()};
+  Value *Args[] = {Arg0, Arg1};
+  auto *Fn =
+      vc::getAnyDeclaration(M, vc::InternalIntrinsic::add_uus_sat, ArgTypes);
+  auto *Res = Builder.CreateCall(Fn, Args, CI->getName());
+  Res->setDebugLoc(DL);
+  return Res;
+}
+
 // llvm.usub.sat i.e. sat(a - b) we can treat as sat(a + (-b))
 // i.e. we are building -b and then uadd with saturation
 bool GenXLowering::lowerUSubWithSat(CallInst *CI) {
   IGC_ASSERT(CI);
   Value *Arg0 = CI->getArgOperand(0);
   Value *Arg1 = IRBuilder<>(CI).CreateNeg(CI->getArgOperand(1), CI->getName());
-  auto *UUAddInst = buildUAddWithSat(CI, Arg0, Arg1, CI, /*IsSignedSrc*/ true);
-  CI->replaceAllUsesWith(UUAddInst);
+  Value *Res = buildUUSAddWithSat(CI, Arg0, Arg1, CI);
+  CI->replaceAllUsesWith(Res);
   ToErase.push_back(CI);
   return true;
 }

IGC/VectorCompiler/lib/GenXCodeGen/Utils/cisa_gen_intrinsics.json

@@ -151,6 +151,15 @@
       "src0": [ "GENERAL", 1 ],
       "src1": [ "GENERAL", 2 ]
     },
+    "vc::InternalIntrinsic::add_uus_sat": {
+      "opc": "ISA_ADD",
+      "exec_size": [ "EXECSIZE" ],
+      "elementwise": [ "ELEMENTWISE" ],
+      "pred": [ "IMPLICITPRED" ],
+      "dst": [ "GENERAL", "UNSIGNED", "SATURATION_SATURATE", 0 ],
+      "src0": [ "GENERAL", "UNSIGNED", "MODIFIER_ARITH", 1 ],
+      "src1": [ "GENERAL", "SIGNED", "MODIFIER_ARITH", 2 ]
+    },
     "vc::InternalIntrinsic::cast_from_bf16": {
       "opc": "ISA_MOV",
       "exec_size": [ "EXECSIZE" ],

IGC/VectorCompiler/test/Lowering/llvm-intrinsics.ll

@@ -94,7 +94,7 @@ define i32 @test_usub_sat(i32 %a, i32 %b)
   %res = tail call i32 @llvm.usub.sat.i32(i32 %a, i32 %b)
 ; COM: this one is in terms on uuadd.sat
 ; CHECK: [[NOTVAL:%[^ ]+]] = sub i32 0, %b
-; CHECK: call i32 @llvm.genx.usadd.sat.i32.i32(i32 %a, i32 [[NOTVAL]])
+; CHECK: call i32 @llvm.vc.internal.add.uus.sat.i32.i32(i32 %a, i32 [[NOTVAL]])
   ret i32 %res
 }
 
@@ -203,4 +203,4 @@ define internal spir_func void @cttz_ctlz_i16(i16 %arg) {
 
   %2 = call i16  @llvm.ctlz.i16(i16 %arg, i1 false)
   ret void
-}
+}