Skip to content

Commit dcc6f77

Browse files
ichenkaiigcbot
authored andcommitted
Fix issue in emit pattern with LVN matching for And
Fix issue with LVN matching for And when in SIMD32 with mad operation.
1 parent 8eb1fe4 commit dcc6f77

File tree

1 file changed

+19
-7
lines changed

1 file changed

+19
-7
lines changed

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5488,18 +5488,30 @@ void EmitPass::emitSimdShuffle(llvm::Instruction *inst) {
54885488
if (defaultConditions || forcePreventOOB) {
54895489
uint maskOfValidLanes = numLanes(m_currShader->m_State.m_dispatchSize) - 1;
54905490

5491-
// To support conversion to movi we need to make all calculations
5492-
// (shl, addr_add) of address NoMask. to avoid random data from
5493-
// previous execution in divergent CF.
5491+
// To support conversion to movi we need to make all calculations (shl, addr_add) of address NoMask.
5492+
// to avoid random data from previous execution in divergent CF.
54945493
if (forcePreventOOB) {
54955494
m_encoder->SetNoMask();
54965495
}
5497-
CVariable *tempCopy = m_currShader->GetNewVariable(simdChannel, "SanitizedIndexShuffleTmp");
54985496

5499-
m_encoder->And(tempCopy, simdChannel, m_currShader->ImmToVariable(maskOfValidLanes, ISA_TYPE_UW));
5500-
m_encoder->Push();
5497+
bool bAllowLVNMatchingForAnd = true;
5498+
if (isSimd32 && data->GetType() == ISA_TYPE_F) {
5499+
if (auto *prevInst = dyn_cast<llvm::Instruction>(inst->getPrevNode()))
5500+
if (GetOpCode(prevInst) == EOPCODE::llvm_fadd)
5501+
bAllowLVNMatchingForAnd = false;
5502+
}
55015503

5502-
simdChannelUW = m_currShader->BitCast(tempCopy, ISA_TYPE_UW);
5504+
if (bAllowLVNMatchingForAnd) {
5505+
CVariable *tempCopy = m_currShader->GetNewVariable(simdChannel, "SanitizedIndexShuffleTmp");
5506+
m_encoder->And(tempCopy, simdChannel, m_currShader->ImmToVariable(maskOfValidLanes, ISA_TYPE_UW));
5507+
simdChannelUW = m_currShader->BitCast(tempCopy, ISA_TYPE_UW);
5508+
}
5509+
else {
5510+
m_encoder->SetSrcRegion(0, 2, 1, 0);
5511+
m_encoder->SetDstRegion(2);
5512+
m_encoder->And(simdChannelUW, simdChannelUW, m_currShader->ImmToVariable(maskOfValidLanes, ISA_TYPE_UW));
5513+
}
5514+
m_encoder->Push();
55035515
}
55045516
CVariable *pSrcElm = m_currShader->GetNewVariable(simdChannel->GetNumberElement(), ISA_TYPE_UW, EALIGN_GRF,
55055517
channelUniform, simdChannel->GetNumberInstance(), "ShuffleTmp");

0 commit comments

Comments
 (0)