Pre-assign GRF to spillHeader in fail safe RA iteration

spillHeader may be used to store offset for spill/fill instruction. It
must be infinite spill cost variable. If spillHeader gets assigned to a
register that causes fragmentation, then it could cause previously
spilled variables to not get an allocation in fail safe RA iteration.

With this change, we find first GRF candidate that can be assigned to
spillHeader. This way, we avoid fragmenting free GRF space.

Author: pratikashar

visa/GraphColor.cpp

@@ -6763,7 +6763,7 @@ void GraphColor::removeConstrained() {
 void GraphColor::determineColorOrdering() {
   numColor = 0;
   if (liveAnalysis.livenessClass(G4_GRF))
-    numColor = totalGRFRegCount - reserveSpillGRFCount;
+    numColor = totalGRFRegCount;
   else if (liveAnalysis.livenessClass(G4_ADDRESS))
     numColor = builder.getNumAddrRegisters();
   else if (liveAnalysis.livenessClass(G4_FLAG))
@@ -7628,6 +7628,10 @@ bool GraphColor::regAlloc(bool doBankConflictReduction,
   intf.init();
   intf.computeInterference();
 
+  if (reserveSpillGRFCount) {
+    preAssignSpillHeader();
+  }
+
   builder.getFreqInfoManager().initForRegAlloc(&liveAnalysis);
 
   // If option is true, try to get extra interference info from file
@@ -10917,6 +10921,49 @@ std::pair<unsigned, unsigned> GlobalRA::reserveGRFSpillReg(GraphColor &coloring)
   return std::make_pair(spillRegSize, indrSpillRegSize);
 }
 
+void GraphColor::preAssignSpillHeader() {
+  // If spill header is used for spill/fill offset, it must have infinite spill
+  // cost. When running fail safe RA, if we assign this range to middle of free
+  // GRF space, it could cause fragmentation and other spilled ranges may not
+  // get an allocation. So, we pre-assign this variable at first candidate GRF
+  // to avoid fragmentation. This is relevant only in fail safe RA iteration.
+  if (!builder.hasValidSpillFillHeader())
+    return;
+
+  std::vector<bool> FreeGRFs(kernel.getNumRegTotal(), true);
+  auto *spillHeader = builder.getSpillFillHeader();
+  if (spillHeader->getRegVar()->getPhyReg())
+    return;
+  unsigned spillHeaderId = spillHeader->getRootDeclare()->getRegVar()->getId();
+  // Compute free GRFs
+  const auto *intf = getIntf();
+  for (auto neighbor : intf->getSparseIntfForVar(spillHeaderId)) {
+    auto *neighborLR = getLiveRanges()[neighbor];
+    auto *neighborGRF = neighborLR->getPhyReg();
+    if (!neighborGRF)
+      continue;
+    unsigned int neighborGRFStart = neighborGRF->asGreg()->getRegNum();
+    unsigned int neighborLastGRF =
+        neighborGRFStart + neighborLR->getNumRegNeeded();
+    for (unsigned int i = neighborGRFStart; i != neighborLastGRF; ++i) {
+      FreeGRFs[i] = false;
+    }
+  }
+
+  // Find a GRF r1 onwards that can be pre-assigned to spillHeader.
+  // r0 is usually reserved.
+  for (unsigned int i = 1; i != FreeGRFs.size(); ++i) {
+    if (FreeGRFs[i]) {
+      // Attach assignment to temp LR and to G4_RegVar
+      getLiveRanges()[spillHeaderId]->setPhyReg(regPool.getGreg(i), 0);
+      spillHeader->getRegVar()->setPhyReg(regPool.getGreg(i), 0);
+      // Decrement counter as this is used later in determineColorOrdering
+      liveAnalysis.reduceNumUnassignedVar();
+      break;
+    }
+  }
+}
+
 // pre-allocate the bits for forbidden registers which will not be used in
 // register assignment.
 // Note that the order of the calls matters, as all RCs inherit from RESERVEDGRF

visa/GraphColor.h

@@ -1165,6 +1165,7 @@ class GraphColor {
                          unsigned execSize);
 
   void gatherScatterForbiddenWA();
+  void preAssignSpillHeader();
 
 public:
   void getExtraInterferenceInfo();

visa/RegAlloc.h

@@ -152,6 +152,7 @@ class LivenessAnalysis {
   unsigned getNumSplitVar() const { return numSplitVar; }
   unsigned getNumSplitStartID() const { return numSplitStartID; }
   unsigned getNumUnassignedVar() const { return numUnassignedVarId; }
+  void reduceNumUnassignedVar() { --numUnassignedVarId; }
   void dump() const;
   void dumpBB(G4_BB *bb) const;
   void dumpLive(BitSet &live) const;