Emit predefined runtime symbol to ZEBinary's symbol table

igorban-intel · igcbot · commit e31c8e92f9f8 · 2024-10-23T17:53:56.000+02:00
.
diff --git a/IGC/AdaptorOCL/OCL/sp/zebin_builder.cpp b/IGC/AdaptorOCL/OCL/sp/zebin_builder.cpp
@@ -420,6 +420,9 @@ void ZEBinaryBuilder::addRuntimeSymbols(const IGC::SOpenCLProgramInfo& annotatio
     if (annotations.m_hasCrossThreadOffsetRelocations)
         mBuilder.addSymbol(vISA::CROSS_THREAD_OFF_R0_RELOCATION_NAME, /*addr*/0, /*size*/0,
             llvm::ELF::STB_GLOBAL, llvm::ELF::STT_NOTYPE, /*sectionId*/-1);
+    if (annotations.m_hasPerThreadOffsetRelocations)
+        mBuilder.addSymbol(vISA::PER_THREAD_OFF_RELOCATION_NAME, /*addr*/0, /*size*/0,
+            llvm::ELF::STB_GLOBAL, llvm::ELF::STT_NOTYPE, /*sectionId*/-1);
 }
 
 void ZEBinaryBuilder::addProgramSymbols(const IGC::SOpenCLProgramInfo& annotations)
@@ -883,12 +886,12 @@ void ZEBinaryBuilder::addElfSections(void* elfBin, size_t elfSize)
                                 }
 
                                 unsigned int relocType = relocEntry.r_info & 0xF;
-                                zebin::R_TYPE_ZEBIN zebinType = R_ZE_NONE;
+                                zebin::R_TYPE_ZEBIN zebinType = R_NONE;
 
                                 if (relocType == ELF::R_X86_64_64)
-                                    zebinType = R_ZE_SYM_ADDR;
+                                    zebinType = R_SYM_ADDR;
                                 else if (relocType == ELF::R_X86_64_32)
-                                    zebinType = R_ZE_SYM_ADDR_32;
+                                    zebinType = R_SYM_ADDR_32;
                                 else
                                     IGC_ASSERT_MESSAGE(false, "Unsupported ELF relocation type");
 
diff --git a/IGC/Compiler/CISACodeGen/CISABuilder.cpp b/IGC/Compiler/CISACodeGen/CISABuilder.cpp
@@ -6866,7 +6866,11 @@ namespace IGC
                     IGC_ASSERT(context->type == ShaderType::OPENCL_SHADER);
                     auto cl_context = static_cast<OpenCLProgramContext*>(context);
                     cl_context->m_programInfo.m_hasCrossThreadOffsetRelocations = true;
-                    break;
+                }
+                else if (reloc.r_symbol == vISA::PER_THREAD_OFF_RELOCATION_NAME) {
+                    IGC_ASSERT(context->type == ShaderType::OPENCL_SHADER);
+                    auto cl_context = static_cast<OpenCLProgramContext*>(context);
+                    cl_context->m_programInfo.m_hasPerThreadOffsetRelocations = true;
                 }
             }
         }
diff --git a/IGC/Compiler/CodeGenPublic.h b/IGC/Compiler/CodeGenPublic.h
@@ -692,6 +692,7 @@ namespace IGC
         LegacySymbolTable m_legacySymbolTable;
         ZEBinGlobalHostAccessTable m_zebinGlobalHostAccessTable;
         bool m_hasCrossThreadOffsetRelocations = false;
+        bool m_hasPerThreadOffsetRelocations = false;
     };
 
     class CBTILayout
diff --git a/IGC/VectorCompiler/igcdeps/include/vc/igcdeps/cmc.h b/IGC/VectorCompiler/igcdeps/include/vc/igcdeps/cmc.h
@@ -147,6 +147,7 @@ class CGen8CMProgram : public iOpenCL::CGen8OpenCLProgramBase {
                    unsigned pointerSizeInBytes) override;
   bool HasErrors() const { return !m_ErrorLog.empty(); };
   bool HasCrossThreadOffsetRelocations();
+  bool HasPerThreadOffsetRelocations();
   llvm::Error GetError() const;
 
   // CM kernel list.
diff --git a/IGC/VectorCompiler/igcdeps/src/PatchTokens.cpp b/IGC/VectorCompiler/igcdeps/src/PatchTokens.cpp
@@ -236,3 +236,14 @@ bool CGen8CMProgram::HasCrossThreadOffsetRelocations() {
   }
   return false;
 }
+
+bool CGen8CMProgram::HasPerThreadOffsetRelocations() {
+  for (const auto &kernel : m_kernels) {
+    for (const auto &reloc : kernel->getProgramOutput().m_relocs) {
+      if (reloc.r_symbol == vISA::PER_THREAD_OFF_RELOCATION_NAME) {
+        return true;
+      }
+    }
+  }
+  return false;
+}
diff --git a/IGC/VectorCompiler/igcdeps/src/cmc.cpp b/IGC/VectorCompiler/igcdeps/src/cmc.cpp
@@ -997,7 +997,8 @@ getDataAnnotation(const GenXOCLRuntimeInfo::DataInfo &Data) {
 static void
 fillOCLProgramInfo(IGC::SOpenCLProgramInfo &ProgramInfo,
                    const GenXOCLRuntimeInfo::ModuleInfoT &ModuleInfo,
-                   bool HasCrossThreadOffsetRelocations) {
+                   bool HasCrossThreadOffsetRelocations,
+                   bool HasPerThreadOffsetRelocations) {
   auto ConstantAnnotation = getDataAnnotation<iOpenCL::InitConstantAnnotation>(
       ModuleInfo.Constant.Data);
   if (ConstantAnnotation)
@@ -1033,6 +1034,7 @@ fillOCLProgramInfo(IGC::SOpenCLProgramInfo &ProgramInfo,
       ModuleInfo.ConstString.Relocations.empty(),
       "relocations inside constant string section are not supported");
   ProgramInfo.m_hasCrossThreadOffsetRelocations = HasCrossThreadOffsetRelocations;
+  ProgramInfo.m_hasPerThreadOffsetRelocations  = HasPerThreadOffsetRelocations;
 };
 
 void vc::createBinary(
@@ -1045,5 +1047,6 @@ void vc::createBinary(
     CMProgram.m_kernels.push_back(std::move(K));
   }
   fillOCLProgramInfo(*CMProgram.m_programInfo, CompiledModule.ModuleInfo,
-      CMProgram.HasCrossThreadOffsetRelocations());
+      CMProgram.HasCrossThreadOffsetRelocations(),
+      CMProgram.HasPerThreadOffsetRelocations());
 }
diff --git a/IGC/ZEBinWriter/zebin/source/ZEELF.h b/IGC/ZEBinWriter/zebin/source/ZEELF.h
@@ -41,10 +41,14 @@ enum SHT_ZEBIN : uint32_t
 // ELF relocation type for ELF32_Rel::ELF32_R_TYPE
 enum R_TYPE_ZEBIN
 {
-    R_ZE_NONE           = 0,
-    R_ZE_SYM_ADDR       = 1, // 64-bit type address
-    R_ZE_SYM_ADDR_32    = 2, // lower 32-bit of 64-bit address.
-    R_ZE_SYM_ADDR_32_HI = 3  // higher 32bits of 64-bit address
+    R_NONE = 0,
+    R_SYM_ADDR = 1,       // 64-bit type address
+    R_SYM_ADDR_32 = 2,    // 32-bit address or lower 32-bit of a 64-bit address.
+    R_SYM_ADDR_32_HI = 3, // higher 32 bits of 64-bit address
+    R_PER_THREAD_PAYLOAD_OFFSET_32 = 4, // *** Deprecated. Do Not Use. ***
+    R_GLOBAL_IMM_32 = 5,  // 32-bit global immediate
+    R_SEND = 6,           // send instruction offset, used for BTI patching
+    R_SYM_ADDR_16 = 7     // 16-bit address or immediate
 };
 
 // ELF note type for INTELGT
diff --git a/IGC/ZEBinWriter/zebin/source/autogen/ZEInfo.hpp b/IGC/ZEBinWriter/zebin/source/autogen/ZEInfo.hpp
@@ -290,7 +290,7 @@ struct zeInfoContainer
     KernelsCostInfoTy kernels_cost_info;
 };
 struct PreDefinedAttrGetter{
-    static zeinfo_str_t getVersionNumber() { return "1.49"; }
+    static zeinfo_str_t getVersionNumber() { return "1.48"; }
 
     enum class ArgThreadSchedulingMode {
         age_based,
diff --git a/IGC/ZEBinWriter/zebin/spec/elf.md b/IGC/ZEBinWriter/zebin/spec/elf.md
@@ -222,11 +222,14 @@ lower than 2.
 Relocation type for **ELF32_R_TYPE** or **ELF64_R_TYPE**
 ~~~
 enum GenRelocType {
-    R_ZE_NONE                      = 0,
-    R_ZE_SYM_ADDR                  = 1, // 64-bit address
-    R_ZE_SYM_ADDR_32               = 2, // 32-bit address or lower 32-bit of a 64-bit address
-    R_ZE_SYM_ADDR_32_HI            = 3  // higher 32bits of a 64-bit address
-    R_PER_THREAD_PAYLOAD_OFFSET_32 = 4  // 32-bit field of payload offset of per-thread data
+    R_NONE                         = 0,
+    R_SYM_ADDR                     = 1, // 64-bit address
+    R_SYM_ADDR_32                  = 2, // 32-bit address or lower 32-bit of a 64-bit address
+    R_SYM_ADDR_32_HI               = 3  // higher 32bits of a 64-bit address
+    R_PER_THREAD_PAYLOAD_OFFSET_32 = 4, // *** Deprecated ***
+    R_GLOBAL_IMM_32                = 5, // 32-bit global immediate
+    R_SEND                         = 6, // send instruction offset, used for BTI patching
+    R_SYM_ADDR_16                  = 7  // 16-bit address or immediate
 };
 ~~~
 
diff --git a/IGC/ZEBinWriter/zebin/spec/version.md b/IGC/ZEBinWriter/zebin/spec/version.md
@@ -7,14 +7,16 @@ SPDX-License-Identifier: MIT
 ============================= end_copyright_notice ==========================-->
 
 # ZEBIN Version
-Version 1.47
+Version 1.48
+=======
 
 ## Versioning
 Format: \<_Major number_\>.\<_Minor number_\>
 - Major number: Increase when non-backward-compatible features are added. For example, rename attributes or remove attributes.
 - Minor number: Increase when backward-compatible features are added. For example, add new attributes.
 
 ## Change Note
+- **Version 1.48**: Add relocation type "R_SYM_ADDR_16" and update supported relocation types.
 - **Version 1.47**: Added kernel cost analysis.
 - **Version 1.46**: Change cmake target directory from IGC/zebinlib to IGC/Libraries/zebinlib
 - **Version 1.45**: Add .text section into ELF section content.
diff --git a/visa/FlowGraph.cpp b/visa/FlowGraph.cpp
@@ -4599,6 +4599,15 @@ uint32_t RelocationEntry::getTargetOffset(const IR_Builder &builder) const {
     vASSERT(opndPos == 1);
     // Src1.imm[31:0] mapped to Instruction [127:96]
     return 12;
+  case G4_mad:
+    vASSERT(relocType == R_SYM_ADDR_16);
+    // Src0.imm[15:0] mapped to Instruction [79:64]
+    // Src2.imm[15:0] mapped to Instruction [127:112]
+    if (opndPos == 1)
+      return 8;
+    else if (opndPos == 3)
+      return 14;
+    break;
   case G4_send:
   case G4_sendc:
   case G4_sends:
@@ -4631,6 +4640,8 @@ const char *RelocationEntry::getTypeString(RelocationType relocType) {
     return "R_GLOBAL_IMM_32";
   case RelocationType::R_SEND:
     return "R_SEND";
+  case RelocationType::R_SYM_ADDR_16:
+    return "R_SYM_ADDR_16";
   default:
     vISA_ASSERT_UNREACHABLE("unhandled relocation type");
     return "??";
diff --git a/visa/PrologEpilog.cpp b/visa/PrologEpilog.cpp
@@ -887,24 +887,22 @@ class PayloadLoader
       // inserted argument), the relocation need to be resolved to the new
       // cross_thread_size.
       G4_Operand *addSrc1 =
-          builder.createRelocImm(GenRelocType::R_PER_THREAD_PAYLOAD_OFFSET_32,
-                                 kernel.getName(), perThreadOffsetMem, Type_UD);
+          builder.createRelocImm(GenRelocType::R_SYM_ADDR_32,
+              PER_THREAD_OFF_RELOCATION_NAME, perThreadOffsetMem, Type_UD);
       auto addDst = builder.createDst(rtmp->getRegVar(), 0, 2, 1, Type_UD);
       // instruction has relocation must not be compacted
       auto addInst =
           builder.createBinOp(G4_add, g4::SIMD1, addDst, addSrc0, addSrc1,
                               InstOpt_WriteEnable | InstOpt_NoCompact, false);
-
-      // FIXME: before RT supports the R_PER_THREAD_PAYLOAD_OFFSET_32 relocation,
-      // we create relocation only when GTPin option is given to avoid the test
-      // failure. We can remove this option check once RT supports it.
-      if (kernel.getOption(vISA_GetFreeGRFInfo)) {
-        // Relocation with the target symbol set to kernel symbol. Note that
-        // currently only ZEBinary will produce kernel symbols
-        RelocationEntry::createRelocation(
-            kernel, *addInst, 1, kernel.getName(),
-            GenRelocType::R_PER_THREAD_PAYLOAD_OFFSET_32);
-      }
+#if 0
+      // disable the relocation entry that gtpin is able to recognize the
+      // instruction pattern and doesn't rely on this relocation. We still mark
+      // addSrc1 as RelocImm (so relocation name is printed in vISA dump), but
+      // the relocation entry won't be emitted to zebin
+      RelocationEntry::createRelocation(builder.kernel, *addInst, 1,
+                                        PER_THREAD_OFF_RELOCATION_NAME,
+                                        GenRelocType::R_SYM_ADDR_32);
+#endif
       instBuffer.push_back(addInst);
 
       if (kernel.getOption(vISA_emitCrossThreadOffR0Reloc)) {
diff --git a/visa/include/RelocationInfo.h b/visa/include/RelocationInfo.h
@@ -24,6 +24,8 @@ namespace vISA {
 static const uint32_t MAX_SYMBOL_NAME_LENGTH = 1024;
 constexpr const char *CROSS_THREAD_OFF_R0_RELOCATION_NAME =
     "__INTEL_PATCH_CROSS_THREAD_OFFSET_OFF_R0";
+constexpr const char *PER_THREAD_OFF_RELOCATION_NAME =
+    "__INTEL_PER_THREAD_OFF";
 
 /// GenSymType - Specify the symbol's type
 enum GenSymType {
@@ -53,9 +55,10 @@ enum GenRelocType {
   R_SYM_ADDR = 1,       // 64-bit type address
   R_SYM_ADDR_32 = 2,    // 32-bit address or lower 32-bit of a 64-bit address.
   R_SYM_ADDR_32_HI = 3, // higher 32 bits of 64-bit address
-  R_PER_THREAD_PAYLOAD_OFFSET_32 = 4, // 32-bit offset of per-thread data
+  R_PER_THREAD_PAYLOAD_OFFSET_32 = 4, // *** Deprecated. Do Not Use. ***
   R_GLOBAL_IMM_32 = 5, // 32-bit global immediate
-  R_SEND = 6 // send instruction offset, used for BTI patching
+  R_SEND = 6, // send instruction offset, used for BTI patching
+  R_SYM_ADDR_16 = 7 // 16-bit address or immediate
 };
 
 /// GenRelocEntry - An relocation table entry

Original file line number	Diff line number	Diff line change
`@@ -6866,7 +6866,11 @@ namespace IGC`
`6866`	`6866`	`IGC_ASSERT(context->type == ShaderType::OPENCL_SHADER);`
`6867`	`6867`	`auto cl_context = static_cast<OpenCLProgramContext*>(context);`
`6868`	`6868`	`cl_context->m_programInfo.m_hasCrossThreadOffsetRelocations = true;`
`6869`		`- break;`
	`6869`	`+ }`
	`6870`	`+ else if (reloc.r_symbol == vISA::PER_THREAD_OFF_RELOCATION_NAME) {`
	`6871`	`+ IGC_ASSERT(context->type == ShaderType::OPENCL_SHADER);`
	`6872`	`+ auto cl_context = static_cast<OpenCLProgramContext*>(context);`
	`6873`	`+ cl_context->m_programInfo.m_hasPerThreadOffsetRelocations = true;`
`6870`	`6874`	`}`
`6871`	`6875`	`}`
`6872`	`6876`	`}`