Add switch to jump table lowering

Author: Anton Sidorenko

IGC/VectorCompiler/include/vc/GenXCodeGen/GenXWrapper.h

@@ -154,6 +154,7 @@ struct CompileOptions {
   bool NoVecDecomp = false;
   bool EmitDebugInfo = false;
 
+  bool NoJumpTables = false;
   OptimizerLevel OptLevel = OptimizerLevel::Full;
   llvm::Optional<unsigned> StackMemSize;
 

IGC/VectorCompiler/include/vc/Support/Options.td

@@ -83,6 +83,9 @@ def no_vector_decomposition_old : Flag<["-"], "no_vector_decomposition">,
   let Flags = [ApiOption, IgcmcApiOption];
 }
 
+def fno_jump_tables : Flag<["-"], "fno-jump-tables">,
+  HelpText<"Disable the use of jump tables for lowering switches">;
+
 def Xfinalizer : Separate<["-"], "Xfinalizer">,
   HelpText<"Pass <arg> to the visa finalizer">, MetaVarName<"<arg>">;
 

IGC/VectorCompiler/lib/GenXCodeGen/CMakeLists.txt

@@ -37,6 +37,7 @@ set(CODEGEN_SOURCES
   GenXLiveness.cpp
   GenXLowering.cpp
   GenXLowerAggrCopies.cpp
+  GenXLowerJmpTableSwitch.cpp
   GenXEmulate.cpp
   GenXModule.cpp
   GenXNumbering.cpp

IGC/VectorCompiler/lib/GenXCodeGen/GenX.h

@@ -81,6 +81,7 @@ FunctionPass *createGenXInstCombineCleanup();
 FunctionPass *createGenXInlineAsmLoweringPass();
 FunctionPass *createGenXLoweringPass();
 FunctionPass *createGenXLowerAggrCopiesPass();
+FunctionPass *createGenXLowerJmpTableSwitchPass();
 FunctionPass *createGenXGEPLoweringPass();
 FunctionPass *createGenXRegionCollapsingPass();
 FunctionPass *createGenXExtractVectorizerPass();

IGC/VectorCompiler/lib/GenXCodeGen/GenX.td

@@ -60,6 +60,12 @@ def FeatureVectorDecomp : SubtargetFeature<"disable_vec_decomp",
                                            "true",
                                            "disable vector decomposition pass">;
 
+def FeatureNoJumpTables : SubtargetFeature<"disable_jump_tables", "DisableJumpTables",
+                                           "true", "disable switch to jump tables lowering">;
+
+def FeatureSwitchjmp : SubtargetFeature<"switchjmp", "HasSwitchjmp", "true",
+                                        "supports switchjmp visa instruction">;
+
 def WarnCallable : SubtargetFeature<"warn_callable", "WarnCallable",
                                     "true", "warn instead of error on callable violation">;
 
@@ -75,16 +81,16 @@ class Proc<string Name, list<SubtargetFeature> Features>
  : Processor<Name, NoItineraries, Features>;
 
 def : Proc<"generic",         []>;
-def : Proc<"HSW",             [FeatureLongLongEmulation]>;
-def : Proc<"BDW",             [FeatureLongLong]>;
-def : Proc<"CHV",             [FeatureLongLong]>;
-def : Proc<"SKL",             [FeatureLongLong]>;
-def : Proc<"BXT",             [FeatureLongLong]>;
-def : Proc<"KBL",             [FeatureLongLong]>;
-def : Proc<"GLK",             [FeatureLongLong]>;
-def : Proc<"CNL",             [FeatureLongLong]>;
-def : Proc<"ICL",             [FeatureLongLong]>;
-def : Proc<"ICLLP",           [FeatureLongLongEmulation]>;
+def : Proc<"HSW",             [FeatureLongLongEmulation, FeatureSwitchjmp]>;
+def : Proc<"BDW",             [FeatureLongLong, FeatureSwitchjmp]>;
+def : Proc<"CHV",             [FeatureLongLong, FeatureSwitchjmp]>;
+def : Proc<"SKL",             [FeatureLongLong, FeatureSwitchjmp]>;
+def : Proc<"BXT",             [FeatureLongLong, FeatureSwitchjmp]>;
+def : Proc<"KBL",             [FeatureLongLong, FeatureSwitchjmp]>;
+def : Proc<"GLK",             [FeatureLongLong, FeatureSwitchjmp]>;
+def : Proc<"CNL",             [FeatureLongLong, FeatureSwitchjmp]>;
+def : Proc<"ICL",             [FeatureLongLong, FeatureSwitchjmp]>;
+def : Proc<"ICLLP",           [FeatureLongLongEmulation, FeatureSwitchjmp]>;
 def : Proc<"TGLLP",           [FeatureLongLongEmulation]>;
 
 def GenX : Target {

IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

@@ -565,6 +565,7 @@ class GenXKernelBuilder {
   void buildControlRegUpdate(unsigned Mask, bool Clear);
   void buildJoin(CallInst *Join, BranchInst *Branch);
   bool buildBranch(BranchInst *Branch);
+  void buildIndirectBr(IndirectBrInst *Br);
   void buildIntrinsic(CallInst *CI, unsigned IntrinID, genx::BaleInfo BI,
                       unsigned Mod, const DstOpndDesc &DstDesc);
   void buildInputs(Function *F, bool NeedRetIP);
@@ -2581,6 +2582,8 @@ bool GenXKernelBuilder::buildMainInst(Instruction *Inst, BaleInfo BI,
     buildRet(RI);
   } else if (BranchInst *BR = dyn_cast<BranchInst>(Inst)) {
     return buildBranch(BR);
+  } else if (IndirectBrInst *IBR = dyn_cast<IndirectBrInst>(Inst)) {
+    buildIndirectBr(IBR);
   } else if (CmpInst *Cmp = dyn_cast<CmpInst>(Inst)) {
     buildCmp(Cmp, BI, DstDesc);
   } else if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Inst)) {
@@ -2650,6 +2653,7 @@ bool GenXKernelBuilder::buildMainInst(Instruction *Inst, BaleInfo BI,
       case GenXIntrinsic::genx_predefined_surface:
       case GenXIntrinsic::genx_output:
       case GenXIntrinsic::genx_output_1:
+      case GenXIntrinsic::genx_jump_table:
         // ignore
         break;
       case GenXIntrinsic::genx_simdcf_goto:
@@ -3764,6 +3768,32 @@ bool GenXKernelBuilder::buildBranch(BranchInst *Branch) {
   return false;
 }
 
+/***********************************************************************
+ * buildIndirectBr : build an indirect branch
+ *
+ * Indirectbr instructions are used only for jump tables.
+ *
+ * Enter:   Br = indirect branch inst
+ */
+void GenXKernelBuilder::buildIndirectBr(IndirectBrInst *Br) {
+  IGC_ASSERT(Subtarget->hasSwitchjmp());
+  Value *Addr = Br->getAddress();
+  auto JumpTable = cast<IntrinsicInst>(Addr);
+  unsigned IID = GenXIntrinsic::getAnyIntrinsicID(JumpTable);
+  IGC_ASSERT(IID == GenXIntrinsic::genx_jump_table);
+  Value *Idx = JumpTable->getArgOperand(0);
+
+  VISA_VectorOpnd *JMPIdx = createSource(Idx, UNSIGNED);
+  unsigned NumDest = Br->getNumDestinations();
+  std::vector<VISA_LabelOpnd *> JMPLabels(NumDest, nullptr);
+  for (unsigned I = 0; I < NumDest; ++I)
+    JMPLabels[I] = Labels[getOrCreateLabel(Br->getDestination(I), LABEL_BLOCK)];
+
+  addDebugInfo();
+  CISA_CALL(
+      Kernel->AppendVISACFSwitchJMPInst(JMPIdx, NumDest, JMPLabels.data()));
+}
+
 /***********************************************************************
  * buildJoin : build a join
  *

IGC/VectorCompiler/lib/GenXCodeGen/GenXLiveness.cpp

@@ -433,15 +433,7 @@ void GenXLiveness::rebuildLiveRangeForValue(LiveRange *LR, SimpleValue SV)
     // all of them at the end).
     *BBRange = Segment(Numbering->getNumber(BB), Num);
     // Push this block's predecessors onto the stack.
-    // (A basic block's predecessors are those blocks containing a
-    // TerminatorInst that uses the basic block.)
-	for (Value::use_iterator i = BB->use_begin(), e = BB->use_end();
-	  i != e; ++i) {
-	  Instruction *TI = dyn_cast<Instruction>(i->getUser());
-      IGC_ASSERT(TI);
-	  if (TI->isTerminator())
-	    Stack.push_back(TI->getParent());
-	}
+    std::copy(pred_begin(BB), pred_end(BB), std::back_inserter(Stack));
     // Process stack until empty.
     while (Stack.size()) {
       BB = Stack.back();
@@ -459,15 +451,7 @@ void GenXLiveness::rebuildLiveRangeForValue(LiveRange *LR, SimpleValue SV)
       // all of them at the end).
       BBRange->setStartEnd(Numbering->getNumber(BB), BBNum->EndNumber);
       // Push this block's predecessors onto the stack.
-      // (A basic block's predecessors are those blocks containing a
-      // TerminatorInst that uses the basic block.)
-	  for (Value::use_iterator i = BB->use_begin(), e = BB->use_end();
- 	    i != e; ++i) {
-		Instruction *TI = dyn_cast<Instruction>(i->getUser());
-        IGC_ASSERT(TI);
-		if (TI->isTerminator())
-		  Stack.push_back(TI->getParent());
-	  }
+      std::copy(pred_begin(BB), pred_end(BB), std::back_inserter(Stack));
     }
   }
   // Now we can build the live range.