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‎IGC/DebugInfo/DwarfCompileUnit.cpp‎

Lines changed: 130 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -698,28 +698,31 @@ void CompileUnit::extractSubRegValue(IGC::DIEBlock *Block, unsigned char Sz) {
698698
addUInt(Block, dwarf::DW_FORM_data1, Sz);
699699
}
700700

701-
// addBindlessOrStatelessLocation - add a sequence of attributes to calculate
702-
// stateless or bindless location of variable. baseAddr is one of the following
703-
// base addreses:
701+
// addBindlessOrStatelessLocation - add a sequence of attributes to calculate stateless or
702+
// bindless location of variable. baseAddr is one of the following base addresses:
704703
// - General State Base Address when variable located in stateless surface
705-
// - Bindless Surface State Base Address when variable located in bindless
706-
// surface
707-
// - Bindless Sampler State Base Addres when variable located in bindless
708-
// sampler Note: Scratch space location is not handled here.
704+
// - Bindless Surface State Base Address when variable located in bindless surface
705+
// - Bindless Sampler State Base Address when variable located in bindless sampler
706+
// Note: Scratch space location is not handled here.
709707
void CompileUnit::addBindlessOrStatelessLocation(IGC::DIEBlock *Block, const VISAVariableLocation &Loc,
710708
uint32_t baseAddrEncoded) {
711709
IGC_ASSERT_MESSAGE(Loc.IsInGlobalAddrSpace(), "Neither bindless nor stateless");
712710
if (Loc.IsRegister()) {
713-
// Stateless surface or bindless surface or bindless sampler with offset not
714-
// available as literal. For example, if offset were available in register
715-
// r0 and we assume the DWARF number of r0 to be 16, the following
716-
// expression can be generated for stateless surface: 1 DW_OP_breg7 0 ,
717-
// breg7 stands for General State Base Address 2 DW_OP_breg16 0 3 DW_OP_plus
711+
// Stateless surface or bindless surface or bindless sampler with offset not available as literal.
712+
// For example, if offset were available in register r0 and we assume the
713+
// DWARF number of r0 to be 16, the following expression can be generated
714+
// for stateless surface:
715+
// 1 DW_OP_breg7 0 , breg7 stands for General State Base Address
716+
// 2 DW_OP_breg16 0
717+
// 3 DW_OP_plus
718718
// or for bindless surface:
719-
// 1 DW_OP_breg9 0 , breg9 stands for Bindless Surface State Base
720-
// Address 2 DW_OP_breg16 0 3 DW_OP_plus or for bindless sampler: 1
721-
// DW_OP_breg10 0 , breg10 stands for Bindless Sampler State Base
722-
// Address 2 DW_OP_breg16 0 3 DW_OP_plus
719+
// 1 DW_OP_breg9 0 , breg9 stands for Bindless Surface State Base Address
720+
// 2 DW_OP_breg16 0
721+
// 3 DW_OP_plus
722+
// or for bindless sampler:
723+
// 1 DW_OP_breg10 0 , breg10 stands for Bindless Sampler State Base Address
724+
// 2 DW_OP_breg16 0
725+
// 3 DW_OP_plus
723726
uint32_t regNum = Loc.GetRegister();
724727
const auto *VISAMod = Loc.GetVISAModule();
725728

@@ -749,13 +752,14 @@ void CompileUnit::addBindlessOrStatelessLocation(IGC::DIEBlock *Block, const VIS
749752
}
750753
if (Loc.HasLocation()) // Is offset available as literal?
751754
{
752-
// Stateless (BTI 255 or 253) addressing using surface offset available as
753-
// literal 1 DW_OP_breg7 <offset> , breg7 stands for General State Base
754-
// Address or Bindless Surface addressing using surface offset available as
755-
// literal 1 DW_OP_breg9 <offset> , breg9 stands for Bindless Surface
756-
// State Base Address or Bindless Sampler addressing using surface offset
757-
// available as literal 1 DW_OP_breg10 <offset> , breg10 stands for
758-
// Bindless Sampler State Base Address
755+
// Stateless (BTI 255 or 253) addressing using surface offset available as literal
756+
// 1 DW_OP_breg7 <offset> , breg7 stands for General State Base Address
757+
// or
758+
// Bindless Surface addressing using surface offset available as literal
759+
// 1 DW_OP_breg9 <offset> , breg9 stands for Bindless Surface State Base Address
760+
// or
761+
// Bindless Sampler addressing using surface offset available as literal
762+
// 1 DW_OP_breg10 <offset> , breg10 stands for Bindless Sampler State Base Address
759763
uint32_t offset = Loc.GetOffset();
760764

761765
addUInt(Block, dwarf::DW_FORM_data1,
@@ -785,13 +789,21 @@ void CompileUnit::addBindlessSurfaceLocation(IGC::DIEBlock *Block, const VISAVar
785789

786790
IGC_ASSERT_MESSAGE(Loc.HasSurface(), "Missing surface for variable location");
787791

788-
// Bindless Surface addressing using bindless offset stored in a register (for
789-
// example) r0, while offset is literal: 1 DW_OP_reg16 2 DW_OP_const1u
790-
// <bit-offset to reg0> 3 DW_OP_const1u 32 4 DW_OP_push_bit_piece_stack 5
791-
// DW_OP_breg9 32 6 DW_OP_plus 7 DW_OP_deref 8 DW_OP_plus_uconst <offset> or
792-
// Bindless Surface addressing using bindless offset and surface offset both
793-
// stored in a register (for example) r0 contains bindless offset while r1
794-
// contains surface offset. 1 DW_OP_reg16 2 DW_OP_const1u <bit-offset to reg0>
792+
// Bindless Surface addressing using bindless offset stored in a register (for example) r0,
793+
// while offset is literal:
794+
// 1 DW_OP_reg16
795+
// 2 DW_OP_const1u <bit-offset to reg0>
796+
// 3 DW_OP_const1u 32
797+
// 4 DW_OP_push_bit_piece_stack
798+
// 5 DW_OP_breg9 32
799+
// 6 DW_OP_plus
800+
// 7 DW_OP_deref
801+
// 8 DW_OP_plus_uconst <offset>
802+
// or
803+
// Bindless Surface addressing using bindless offset and surface offset both stored in a register
804+
// (for example) r0 contains bindless offset while r1 contains surface offset.
805+
// 1 DW_OP_reg16
806+
// 2 DW_OP_const1u <bit-offset to reg0>
795807
// 3 DW_OP_const1u 32
796808
// 4 DW_OP_push_bit_piece_stack
797809
// 5 DW_OP_breg9 32
@@ -860,8 +872,8 @@ void CompileUnit::addBindlessScratchSpaceLocation(IGC::DIEBlock *Block, const VI
860872

861873
IGC_ASSERT_MESSAGE(Loc.HasSurface(), "Missing surface for variable location");
862874

863-
// Note: Bindless scratch space offset aka Scratch Space Pointer is located in
864-
// preserved r0 GRF register, on bits 31:10 of r0.5 subregister.
875+
// Note: Bindless scratch space offset aka Scratch Space Pointer is located in preserved r0 GRF register,
876+
// on bits 31:10 of r0.5 subregister.
865877
//
866878
// Bindless Surface addressing using bindless offset stored in a register r0,
867879
// while surface offset is literal:
@@ -871,17 +883,26 @@ void CompileUnit::addBindlessScratchSpaceLocation(IGC::DIEBlock *Block, const VI
871883
// 4 DW_OP_const4u 0xffffffc0 , which is 1K-byte aligned
872884
// 5 DW_OP_and
873885
// 6 DW_OP_push_bit_piece_stack
874-
// 7 DW_OP_breg8 32 , we add the surface state base address plus
875-
// the field offset 8 DW_OP_plus , to fetch the surface base
876-
// address inside the RENDER_SURFACE_STATE object 9 DW_OP_deref 10
877-
// DW_OP_plus_uconst <offset> or Bindless Surface addressing using bindless
878-
// offset (r0.5 [31:10]) and surface offset both stored in a register while r1
879-
// (for example) contains surface offset. 1 DW_OP_reg16 2 DW_OP_const1u 5*32
880-
// , Offset in bits to r0.5 3 DW_OP_const1u 32 , 32-bit long
881-
// bindless offset 4 DW_OP_const4u 0xffffffc0 , which is 1K-byte aligned 5
882-
// DW_OP_and 6 DW_OP_push_bit_piece_stack 7 DW_OP_breg8 32 8 DW_OP_plus 9
883-
// DW_OP_deref 10 DW_OP_reg17 11 DW_OP_const1u <bit-offset to reg1> 12
884-
// DW_OP_const1u 32 13 DW_OP_push_bit_piece_stack
886+
// 7 DW_OP_breg8 32 , we add the surface state base address plus the field offset
887+
// 8 DW_OP_plus , to fetch the surface base address inside the RENDER_SURFACE_STATE object
888+
// 9 DW_OP_deref
889+
// 10 DW_OP_plus_uconst <offset>
890+
// or
891+
// Bindless Surface addressing using bindless offset (r0.5 [31:10]) and surface offset both stored in a register
892+
// while r1 (for example) contains surface offset.
893+
// 1 DW_OP_reg16
894+
// 2 DW_OP_const1u 5*32 , Offset in bits to r0.5
895+
// 3 DW_OP_const1u 32 , 32-bit long bindless offset
896+
// 4 DW_OP_const4u 0xffffffc0 , which is 1K-byte aligned
897+
// 5 DW_OP_and
898+
// 6 DW_OP_push_bit_piece_stack
899+
// 7 DW_OP_breg8 32
900+
// 8 DW_OP_plus
901+
// 9 DW_OP_deref
902+
// 10 DW_OP_reg17
903+
// 11 DW_OP_const1u <bit-offset to reg1>
904+
// 12 DW_OP_const1u 32
905+
// 13 DW_OP_push_bit_piece_stack
885906

886907
uint16_t regNumWithBindlessOffset = 0; // TBD Bindless offset in GRF
887908

@@ -990,16 +1011,19 @@ void CompileUnit::addScratchLocation(IGC::DIEBlock *Block, uint32_t memoryOffset
9901011
addSInt(Block, dwarf::DW_FORM_sdata, offset); // Offset to base address
9911012
}
9921013

993-
// addSimdLane - add a sequence of attributes to calculate location of
994-
// vectorized variable among SIMD lanes, e.g. a GRF subregister.
1014+
// addSimdLane - add a sequence of attributes to calculate location of vectorized variable
1015+
// among SIMD lanes, e.g. a GRF subregister.
9951016
//
996-
// CASE 1: Example of expression generated for 64-bit (or 32-bit) pointer to a
997-
// variable, which is located in scratch: (note: DW_OP_const8u address is
998-
// generated earlier) DW_OP_INTEL_push_simd_lane DW_OP_lit3 (or lit2 for 32-bit
999-
// ptr) DW_OP_shl DW_OP_plus DW_OP_deref
1017+
// CASE 1: Example of expression generated for 64-bit (or 32-bit) pointer to a variable,
1018+
// which is located in scratch: (note: DW_OP_const8u address is generated earlier)
1019+
// DW_OP_INTEL_push_simd_lane
1020+
// DW_OP_lit3 (or lit2 for 32-bit ptr)
1021+
// DW_OP_shl
1022+
// DW_OP_plus
1023+
// DW_OP_deref
10001024
//
1001-
// CASE 2: Example of expressions generated for 64-bit ptr addresses in SIMD8 or
1002-
// SIMD16: 1 DW_OP_INTEL_push_simd_lane
1025+
// CASE 2: Example of expressions generated for 64-bit ptr addresses in SIMD8 or SIMD16:
1026+
// 1 DW_OP_INTEL_push_simd_lane
10031027
// DW_OP_lit16 <--
10041028
// DW_OP_minus <-- Emitted only for second half of SIMD32 kernels
10051029
// 2 DW_OP_lit2
@@ -1040,9 +1064,12 @@ void CompileUnit::addScratchLocation(IGC::DIEBlock *Block, uint32_t memoryOffset
10401064
// 4 DW_OP_plus_uconst(<n> +16)
10411065
// 5 DW_OP_INTEL_regs
10421066
// 6 DW_OP_INTEL_push_simd_lane
1043-
// 7 DW_OP_lit3 or lit7 or lit15 or lit31 respectively for 64/32/16/8 bit
1044-
// variable 8 DW_OP_and 9 DW_OP_const1u 64 or 32 or 16 or 8 10 DW_OP_mul 11
1045-
// DW_OP_const1u 64 or 32 or 16 or 8 12 DW_OP_INTEL_bit_piece_stack
1067+
// 7 DW_OP_lit3 or lit7 or lit15 or lit31 respectively for 64/32/16/8 bit variable
1068+
// 8 DW_OP_and
1069+
// 9 DW_OP_const1u 64 or 32 or 16 or 8
1070+
// 10 DW_OP_mul
1071+
// 11 DW_OP_const1u 64 or 32 or 16 or 8
1072+
// 12 DW_OP_INTEL_bit_piece_stack
10461073
//
10471074
// CASE 5: Example of expression generated for 16-bit or 8-bit variable unpacked
10481075
// in SIMD8 or SIMD16:
@@ -1085,10 +1112,14 @@ void CompileUnit::addSimdLane(IGC::DIEBlock *Block, const DbgVariable &DV, const
10851112
IGC_ASSERT_MESSAGE(varSizeInBits % 8 == 0, "Variable's size not aligned to byte");
10861113

10871114
if (lr->isSpill()) {
1088-
// CASE 1: Example of expression generated for 64-bit or 32-bit ptr to a
1089-
// variable, which is located in scratch: (note: DW_OP_const8u address is
1090-
// generated earlier) DW_OP_INTEL_push_simd_lane DW_OP_lit3 (or DW_OP_lit2
1091-
// for 32-bit ptr) DW_OP_shl DW_OP_plus DW_OP_deref
1115+
// CASE 1: Example of expression generated for 64-bit or 32-bit ptr to a variable,
1116+
// which is located in scratch:
1117+
// (note: DW_OP_const8u address is generated earlier)
1118+
// DW_OP_INTEL_push_simd_lane
1119+
// DW_OP_lit3 (or DW_OP_lit2 for 32-bit ptr)
1120+
// DW_OP_shl
1121+
// DW_OP_plus
1122+
// DW_OP_deref
10921123

10931124
EmitPushSimdLane(Block, isSecondHalf);
10941125
// *8 if 64-bit ptr or *4 if 32-bit ptr.
@@ -1112,8 +1143,8 @@ void CompileUnit::addSimdLane(IGC::DIEBlock *Block, const DbgVariable &DV, const
11121143
// This case handles the case where a source variable is held in
11131144
// GRF or a ptr to it is held in GRF.
11141145

1115-
// CASE 2 and CASE 3: Expressions generated for 64-bit (or 32-bit) bit ptr
1116-
// addresses in SIMD8 or SIMD16: 1 DW_OP_INTEL_push_simd_lane
1146+
// CASE 2 and CASE 3: Expressions generated for 64-bit (or 32-bit) bit ptr addresses in SIMD8 or SIMD16:
1147+
// 1 DW_OP_INTEL_push_simd_lane
11171148
// DW_OP_lit16 <--
11181149
// DW_OP_minus <-- Emitted only for second half of SIMD32 kernels
11191150
// 2 DW_OP_lit2 (CASE 3: lit3)
@@ -1133,15 +1164,21 @@ void CompileUnit::addSimdLane(IGC::DIEBlock *Block, const DbgVariable &DV, const
11331164
// 1 DW_OP_INTEL_push_simd_lane
11341165
// DW_OP_lit16 <--
11351166
// DW_OP_minus <-- Emitted only for second half of SIMD32 kernels
1136-
// 2 DW_OP_lit2 or lit3 or lit4 or lit5 respectively for 64/32/16/8 bit
1137-
// variable 3 DW_OP_shr 4 DW_OP_plus_uconst(<n> +16) 5 DW_OP_INTEL_regs 6
1138-
// DW_OP_INTEL_push_simd_lane 7 DW_OP_lit3 or lit7 or lit15 or lit31
1139-
// respectively for 64/32/16/8 bit variable 8 DW_OP_and 9 DW_OP_const1u 64
1140-
// or 32 or 16 or 8 10 DW_OP_mul 11 DW_OP_const1u 64 or 32 or 16 or 8 12
1141-
// DW_OP_INTEL_bit_piece_stack
1167+
// 2 DW_OP_lit2 or lit3 or lit4 or lit5 respectively for 64/32/16/8 bit variable
1168+
// 3 DW_OP_shr
1169+
// 4 DW_OP_plus_uconst(<n> +16)
1170+
// 5 DW_OP_INTEL_regs
1171+
// 6 DW_OP_INTEL_push_simd_lane
1172+
// 7 DW_OP_lit3 or lit7 or lit15 or lit31 respectively for 64/32/16/8 bit variable
1173+
// 8 DW_OP_and
1174+
// 9 DW_OP_const1u 64 or 32 or 16 or 8
1175+
// 10 DW_OP_mul
1176+
// 11 DW_OP_const1u 64 or 32 or 16 or 8
1177+
// 12 DW_OP_INTEL_bit_piece_stack
11421178
//
1143-
// CASE 5: Example of expression generated for 16-bit or 8-bit variable
1144-
// unpacked in SIMD8 or SIMD16: 1 DW_OP_INTEL_push_simd_lane
1179+
// CASE 5: Example of expression generated for 16-bit or 8-bit variable unpacked
1180+
// in SIMD8 or SIMD16:
1181+
// 1 DW_OP_INTEL_push_simd_lane
11451182
// DW_OP_lit16 <--
11461183
// DW_OP_minus <-- Emitted only for second half of SIMD32 kernels
11471184
// 2 DW_OP_lit3
@@ -1156,8 +1193,7 @@ void CompileUnit::addSimdLane(IGC::DIEBlock *Block, const DbgVariable &DV, const
11561193
// 11 DW_OP_const1u 16 or 8
11571194
// 12 DW_OP_INTEL_piece_stack
11581195

1159-
// If unpacked then small variable takes up 32 bits else when packed fits
1160-
// its exact size
1196+
// If unpacked then small variable takes up 32 bits else when packed fits its exact size
11611197
uint32_t bitsUsedByVar = (isPacked || varSizeInBits > 32) ? (uint32_t)varSizeInBits : 32;
11621198
uint32_t variablesInSingleGRF = (VISAMod->getGRFSizeInBits()) / bitsUsedByVar;
11631199
uint32_t valForSubRegLit = variablesInSingleGRF > 0 ? (uint32_t)std::log2(variablesInSingleGRF) : 0;
@@ -2184,17 +2220,22 @@ bool CompileUnit::buildPrivateBaseRegBased(const DbgVariable &var, IGC::DIEBlock
21842220
// %Y = privateBase (%X)
21852221
// + (%perThreadOffset + (simdSize * <variable offset>)
21862222
// + (simdLaneId * <variable size>))
2187-
// CASE with Private Base and Per Thread Offset in GRF registers (both not
2188-
// spilled) 1 DW_OP_regx <Private Base reg encoded> 2 DW_OP_const1u/2u
2189-
// <bit-offset to Private Base reg> 3 DW_OP_const1u 64 , i.e. size on bits 4
2190-
// DW_OP_INTEL_push_bit_piece_stack 5 DW_OP_constu <Per Thread reg encoded> 6
2191-
// DW_OP_INTEL_regs , i.e. Per Thread Offset 7 DW_OP_const1u <bit-offset
2192-
// to Per Thread Offset> 8 DW_OP_const1u 32 , i.e. size in bits 9
2193-
// DW_OP_INTEL_push_bit_piece_stack 10 DW_OP_plus , i.e. add Private Base to
2194-
// Per Thread Offset 11 DW_OP_plus_uconst offset , i.e. simdSize * <variable
2195-
// offset> 12 DW_OP_INTEL_push_simd_lane 13 DW_OP_const1u/2u/4u/8u
2196-
// <variableSize> , i.e. size in bytes 14 DW_OP_mul 15 DW_OP_plus
2197-
// 16 remaining opcodes from DIExpression
2223+
// CASE with Private Base and Per Thread Offset in GRF registers (both not spilled)
2224+
// 1 DW_OP_regx <Private Base reg encoded>
2225+
// 2 DW_OP_const1u/2u <bit-offset to Private Base reg>
2226+
// 3 DW_OP_const1u 64 , i.e. size on bits
2227+
// 4 DW_OP_INTEL_push_bit_piece_stack
2228+
// 5 DW_OP_constu <Per Thread reg encoded>
2229+
// 6 DW_OP_INTEL_regs , i.e. Per Thread Offset
2230+
// 7 DW_OP_const1u <bit-offset to Per Thread Offset>
2231+
// 8 DW_OP_const1u 32 , i.e. size in bits
2232+
// 9 DW_OP_INTEL_push_bit_piece_stack
2233+
// 10 DW_OP_plus , i.e. add Private Base to Per Thread Offset
2234+
// 11 DW_OP_plus_uconst offset , i.e. simdSize * <variable offset>
2235+
// 12 DW_OP_INTEL_push_simd_lane
2236+
// 13 DW_OP_const1u/2u/4u/8u <variableSize> , i.e. size in bytes
2237+
// 14 DW_OP_mul
2238+
// 15 DW_OP_plus
21982239
auto simdSize = VISAMod->GetSIMDSize();
21992240

22002241
// Rely on getVarInfo result here.
@@ -2321,12 +2362,14 @@ bool CompileUnit::buildFpBasedLoc(const DbgVariable &var, IGC::DIEBlock *Block,
23212362
// 2 DW_OP_const1u <bit-offset to Frame Pointer reg>
23222363
// 3 DW_OP_const1u 64 , i.e. size in bits
23232364
// 4 DW_OP_INTEL_push_bit_piece_stack
2324-
// 5 DW_OP_plus_uconst SIZE_OWORD // i.e. 0x10 taken from
2325-
// getFPOffset(); same as emitted in EmitPass::emitStackAlloca() 6
2326-
// DW_OP_push_simd_lane 7 DW_OP_const1u/2u/4u/8u storageSize // MD:
2327-
// StorageSize; the size of the variable 8 DW_OP_mul 9 DW_OP_plus 10
2328-
// DW_OP_plus_uconst storageOffset // MD: StorageOffset; the offset where
2329-
// each variable is stored in the current stack frame
2365+
// 5 DW_OP_plus_uconst SIZE_OWORD -- i.e. 0x10 taken from getFPOffset();
2366+
// same as emitted in EmitPass::emitStackAlloca()
2367+
// 6 DW_OP_push_simd_lane
2368+
// 7 DW_OP_const1u/2u/4u/8u storageSize -- MD: StorageSize; the size of the variable
2369+
// 8 DW_OP_mul
2370+
// 9 DW_OP_plus
2371+
// 10 DW_OP_plus_uconst storageOffset -- MD: StorageOffset; the offset where each
2372+
// variable is stored in the current stack frame
23302373

23312374
auto regNumFP = VISAMod->getFPReg();
23322375

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