@@ -3418,6 +3418,12 @@ bool Augmentation::markNonDefaultMaskDef()
34183418 nonDefaultMaskDefFound = true ;
34193419 }
34203420
3421+ if (kernel.getOption (vISA_enableBCR) && gra.getBankConflict (dcl) != BANK_CONFLICT_NONE)
3422+ {
3423+ gra.setAugmentationMask (dcl, AugmentationMasks::NonDefault);
3424+ nonDefaultMaskDefFound = true ;
3425+ }
3426+
34213427 if (!nonDefaultMaskDefFound &&
34223428 gra.getAugmentationMask (dcl) != prevAugMask &&
34233429 prevAugMask != AugmentationMasks::Undetermined)
@@ -6084,7 +6090,7 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF, bool doBankConfl
60846090 //
60856091 // for GRF register assignment, if we are performing round-robin (1st pass) then abort on spill
60866092 //
6087- if ((heuristic == ROUND_ROBIN || doBankConflict) &&
6093+ if ((heuristic == ROUND_ROBIN || ( doBankConflict && !kernel. getOption (vISA_enableBCR)) ) &&
60886094 (lr->getRegKind () == G4_GRF || lr->getRegKind () == G4_FLAG))
60896095 {
60906096 return false ;
@@ -6659,10 +6665,13 @@ bool GraphColor::regAlloc(
66596665 return false ;
66606666 }
66616667
6662- if (!success && doBankConflictReduction )
6668+ if (!kernel. getOption (vISA_enableBCR) )
66636669 {
6664- resetTemporaryRegisterAssignments ();
6665- assignColors (FIRST_FIT, false , false );
6670+ if (!success && doBankConflictReduction)
6671+ {
6672+ resetTemporaryRegisterAssignments ();
6673+ assignColors (FIRST_FIT, false , false );
6674+ }
66666675 }
66676676 }
66686677 }
@@ -9811,7 +9820,6 @@ int GlobalRA::coloringRegAlloc()
98119820 failSafeRAIteration++;
98129821 }
98139822 }
9814-
98159823 stopTimer (TimerID::SPILL);
98169824 }
98179825 // RA successfully allocates regs
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