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mshelegoigcbot
mshelego
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igcbot
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Change default float controls
Switch default denormals handling from flush-to-zero into retain
1 parent 40597da commit f0080c8

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4 files changed

+41
-28
lines changed

4 files changed

+41
-28
lines changed

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXFloatControl.cpp‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*========================== begin_copyright_notice ============================
22
3-
Copyright (C) 2024 Intel Corporation
3+
Copyright (C) 2024-2025 Intel Corporation
44
55
SPDX-License-Identifier: MIT
66
@@ -66,8 +66,10 @@ bool GenXFloatControl::runOnFunction(Function &F) {
6666
CRBits::SinglePrecisionDenorm | CRBits::HalfPrecisionDenorm;
6767
// Default float control:
6868
// rounding mode = nearest even
69-
// denormals = flush
70-
uint32_t FloatControl = CRBits::RTNE;
69+
// denormals = retain
70+
uint32_t FloatControl = CRBits::RTNE | CRBits::DoublePrecisionDenorm |
71+
CRBits::SinglePrecisionDenorm |
72+
CRBits::HalfPrecisionDenorm;
7173
const auto *Subtarget = &getAnalysis<TargetPassConfig>()
7274
.getTM<GenXTargetMachine>()
7375
.getGenXSubtarget();

‎IGC/VectorCompiler/test/GenXFloatControl/float_control.ll‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
22
;
3-
; Copyright (C) 2024 Intel Corporation
3+
; Copyright (C) 2024-2025 Intel Corporation
44
;
55
; SPDX-License-Identifier: MIT
66
;
@@ -18,10 +18,19 @@
1818
; RUN: FileCheck %s --check-prefix=CHECK-VISA
1919

2020
; CHECK-LABEL: define dllexport spir_kernel void @kernel
21-
; CHECK-NOT: predef
21+
; CHECK-NEXT: [[AND_READ_PREDEF:[^ ]+]] = call <4 x i32> @llvm.genx.read.predef.reg.v4i32.v4i32(i32 14, <4 x i32> undef)
22+
; CHECK-NEXT: [[AND_RDREGION:[^ ]+]] = call i32 @llvm.genx.rdregioni.i32.v4i32.i16(<4 x i32> [[AND_READ_PREDEF]], i32 0, i32 1, i32 1, i16 0, i32 undef)
23+
; CHECK-NEXT: [[AND:[^ ]+]] = and i32 [[AND_RDREGION]], -1265
24+
; CHECK-NEXT: [[AND_WRREGION:[^ ]+]] = call <4 x i32> @llvm.genx.wrregioni.v4i32.i32.i16.i1(<4 x i32> [[AND_READ_PREDEF]], i32 [[AND]], i32 0, i32 1, i32 1, i16 0, i32 undef, i1 true)
25+
; CHECK-NEXT: call <4 x i32> @llvm.genx.write.predef.reg.v4i32.v4i32(i32 14, <4 x i32> [[AND_WRREGION]])
26+
; CHECK-NEXT: [[OR_READ_PREDEF:[^ ]+]] = call <4 x i32> @llvm.genx.read.predef.reg.v4i32.v4i32(i32 14, <4 x i32> undef)
27+
; CHECK-NEXT: [[OR_RDREGION:[^ ]+]] = call i32 @llvm.genx.rdregioni.i32.v4i32.i16(<4 x i32> [[OR_READ_PREDEF]], i32 0, i32 1, i32 1, i16 0, i32 undef)
28+
; CHECK-NEXT: [[OR:[^ ]+]] = or i32 [[OR_RDREGION]], 1216
29+
; CHECK-NEXT: [[OR_WRREGION:[^ ]+]] = call <4 x i32> @llvm.genx.wrregioni.v4i32.i32.i16.i1(<4 x i32> [[OR_READ_PREDEF]], i32 [[OR]], i32 0, i32 1, i32 1, i16 0, i32 undef, i1 true)
2230
; CHECK: ret
2331
; CHECK-VISA-LABEL: .function "kernel_BB_0"
24-
; CHECK-VISA-NOT: %cr0
32+
; CHECK-VISA: and (M1, 1) %cr0(0,0)<1> %cr0(0,0)<0;1,0> 0xfffffb0f:d
33+
; CHECK-VISA-NEXT: or (M1, 1) %cr0(0,0)<1> %cr0(0,0)<0;1,0> 0x4c0:d
2534
; CHECK-VISA: ret (M1, 1)
2635
define dllexport spir_kernel void @kernel(i32 %a, i64 %privBase) #0 {
2736
call spir_func i32 @stackcall(i32 %a) #1

‎IGC/VectorCompiler/test/VisaRegAlloc/no_coalescing.ll‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
22
;
3-
; Copyright (C) 2021-2024 Intel Corporation
3+
; Copyright (C) 2021-2025 Intel Corporation
44
;
55
; SPDX-License-Identifier: MIT
66
;
@@ -19,17 +19,15 @@
1919
; RUN: -vc-fg-dump-prefix=%basename_t_ \
2020
; RUN: -finalizer-opts='-generateDebugInfo' -o /dev/null
2121

22-
; COM: These checks are brittle and differ between LLVM versions.
23-
; COM: Currently accounted for with {{(<pre-llvm11-val>|<llvm11-val>)}} regexp syntax.
24-
; FIXME: Return unconditional checks once LLVM version is unified for IGC.
25-
2622
; RUN: FileCheck %s --input-file=%basename_t_M_.regalloc --check-prefix=CHECK_NOCOALESC
27-
; CHECK_NOCOALESC: [t7] (4 bytes, length 13) arg1:[0,13)
28-
; CHECK_NOCOALESC-NEXT: [t6] (4 bytes, length 7) arg:[0,7)
29-
; CHECK_NOCOALESC-NEXT: [v32] (64 bytes, length {{(4|6)}}) :[5,{{(9|11)}})
30-
; CHECK_NOCOALESC-NEXT: [v33] (64 bytes, length {{(4|2)}}) :[7,{{(11|9)}})
31-
; CHECK_NOCOALESC-NEXT: [v34] (64 bytes, length 2) :[9,11)
32-
; CHECK_NOCOALESC-NEXt: [v35] (64 bytes, length 2) :[11,13)
23+
; CHECK_NOCOALESC: [t7] (4 bytes, length 33) arg1:[0,33)
24+
; CHECK_NOCOALESC-NEXT: [t6] (4 bytes, length 27) arg:[0,27)
25+
; CHECK_NOCOALESC-NEXT: [v34] (64 bytes, length 6) :[25,31)
26+
; CHECK_NOCOALESC-NEXT: [v32] (16 bytes, length 3) :[10,13)
27+
; CHECK_NOCOALESC-NEXT: [v33] (16 bytes, length 3) :[20,23)
28+
; CHECK_NOCOALESC-NEXT: [v35] (64 bytes, length 2) :[27,29)
29+
; CHECK_NOCOALESC-NEXT: [v36] (64 bytes, length 2) :[29,31)
30+
; CHECK_NOCOALESC-NEXT: [v37] (64 bytes, length 2) :[31,33)
3331
; CHECK_NOCOALESC: Register pressure (bytes):
3432
; CHECK_NOCOALESC: Flag pressure (bytes):
3533

@@ -45,11 +43,13 @@
4543
; RUN: -finalizer-opts='-generateDebugInfo' -o /dev/null
4644

4745
; RUN: FileCheck %s --input-file=%basename_t_M_.regalloc --check-prefix=CHECK_COALESC
48-
; CHECK_COALESC: [t7] (4 bytes, length 13) arg1:[0,13)
49-
; CHECK_COALESC-NEXT: [t6] (4 bytes, length 7) arg:[0,7)
50-
; CHECK_COALESC-NEXT: [v{{(33|32)}}] (64 bytes, length 6) :[5,11)
51-
; CHECK_COALESC-NEXT: [v{{(32|33)}}] (64 bytes, length 4) :[7,11)
52-
; CHECK_COALESC-NEXt: [v34] (64 bytes, length 2) :[11,13)
46+
; CHECK_COALESC: [t7] (4 bytes, length 33) arg1:[0,33)
47+
; CHECK_COALESC-NEXT: [t6] (4 bytes, length 27) arg:[0,27)
48+
; CHECK_COALESC-NEXT: [v34] (64 bytes, length 6) :[25,31)
49+
; CHECK_COALESC-NEXT: [v35] (64 bytes, length 4) :[27,31)
50+
; CHECK_COALESC-NEXT: [v32] (16 bytes, length 3) :[10,13)
51+
; CHECK_COALESC-NEXT: [v33] (16 bytes, length 3) :[20,23)
52+
; CHECK_COALESC-NEXT: [v36] (64 bytes, length 2) :[31,33)
5353
; CHECK_COALESC: Register pressure (bytes):
5454
; CHECK_COALESC: Flag pressure (bytes):
5555

‎IGC/VectorCompiler/test/VisaRegAlloc/reg_alloc_dump_basic.ll‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
22
;
3-
; Copyright (C) 2021-2024 Intel Corporation
3+
; Copyright (C) 2021-2025 Intel Corporation
44
;
55
; SPDX-License-Identifier: MIT
66
;
@@ -20,11 +20,13 @@
2020
; COM: these checks are potentially brittle. Though, the size of the test is
2121
; COM: small and it should be easy to modify if problem arise
2222
; RUN: FileCheck %s --input-file=%basename_t_M_.regalloc
23-
; CHECK: [t7] (4 bytes, length 11) arg1:[0,11)
24-
; CHECK-NEXT: [t6] (4 bytes, length 7) arg:[0,7)
25-
; CHECK-NEXT: [v32] (64 bytes, length 4) :[5,9)
26-
; CHECK-NEXT: [v33] (64 bytes, length 2) :[7,9)
27-
; CHECK-NEXT: [v34] (64 bytes, length 2) :[9,11)
23+
; CHECK: [t7] (4 bytes, length 31) arg1:[0,31)
24+
; CHECK-NEXT: [t6] (4 bytes, length 27) arg:[0,27)
25+
; CHECK-NEXT: [v34] (64 bytes, length 4) :[25,29)
26+
; CHECK-NEXT: [v32] (16 bytes, length 3) :[10,13)
27+
; CHECK-NEXT: [v33] (16 bytes, length 3) :[20,23)
28+
; CHECK-NEXT: [v35] (64 bytes, length 2) :[27,29)
29+
; CHECK-NEXT: [v36] (64 bytes, length 2) :[29,31)
2830
; CHECK: Register pressure (bytes):
2931
; CHECK: Flag pressure (bytes):
3032

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