Update VISA documentation

Author: pszymich

documentation/visa/6_instructions.md

@@ -70,21 +70,21 @@ Arithmetic Instructions
 
 - [DIV - division](instructions/DIV.md)
 
-- [DIVM - IEEE floating point divide {SKL,XEHP+}](instructions/DIVM.md)
+- [DIVM - IEEE floating point divide {XEHP+,SKL}](instructions/DIVM.md)
 
 - [DP4A - dot product 4 accumulate {TGLLP+}](instructions/DP4A.md)
 
 - [DPAS - Dot Product Accumulate Systolic {XEHP+}](instructions/DPAS.md)
 
-- [DPASW - Dot Product Accumulate Systolic Wide {XEHP,DG2}](instructions/DPASW.md)
+- [DPASW - Dot Product Accumulate Systolic Wide {DG2,XEHP}](instructions/DPASW.md)
 
 - [EXP - exponent](instructions/EXP.md)
 
 - [FRC - fraction](instructions/FRC.md)
 
 - [INV - reciprocal](instructions/INV.md)
 
-- [INVM - Div macro {SKL,XEHP+}](instructions/INVM.md)
+- [INVM - Div macro {XEHP+,SKL}](instructions/INVM.md)
 
 - [LOG - logarithm](instructions/LOG.md)
 
@@ -116,7 +116,7 @@ Arithmetic Instructions
 
 - [RSQRT - inverse square root](instructions/RSQRT.md)
 
-- [RSQTM - Inverse square root macro {SKL,XEHP+}](instructions/RSQTM.md)
+- [RSQTM - Inverse square root macro {XEHP+,SKL}](instructions/RSQTM.md)
 
 - [SAD2 - two-wide sum of absolute {-ICLLP}](instructions/SAD2.md)
 
@@ -126,7 +126,7 @@ Arithmetic Instructions
 
 - [SQRT - square root](instructions/SQRT.md)
 
-- [SQRTM - ieee square root {SKL,XEHP+}](instructions/SQRTM.md)
+- [SQRTM - ieee square root {XEHP+,SKL}](instructions/SQRTM.md)
 
 - [SRND - Stochastic round {PVC_XT+}](instructions/SRND.md)
 
@@ -162,7 +162,7 @@ Control Flow Instructions
 
 - [SUBROUTINE - subroutine](instructions/SUBROUTINE.md)
 
-- [SWITCHJMP - switch jump table {-TGLLP,PVC+}](instructions/SWITCHJMP.md)
+- [SWITCHJMP - switch jump table {PVC+,-TGLLP}](instructions/SWITCHJMP.md)
 
 
 Data Movement Instructions
@@ -296,19 +296,19 @@ Surface-based Memory Access Instructions
 SVM - Shared Virtual Memory Access
 ----------------------------------
 
-- [SVM_SCATTER - SMV scatter](instructions/SVM_SCATTER.md)
-
 - [SVM_BLOCK_LD - SMV Block Load](instructions/SVM_BLOCK_LD.md)
 
-- [SVM_ATOMIC - SVM atomic operations](instructions/SVM_ATOMIC.md)
+- [SVM_GATHER - SMV gather](instructions/SVM_GATHER.md)
+
+- [SVM_BLOCK_ST - SMV Block Store](instructions/SVM_BLOCK_ST.md)
 
 - [SVM_GATHER4_SCALED - SVM gather4 with scaling pitch](instructions/SVM_GATHER4_SCALED.md)
 
 - [SVM_SCATTER4_SCALED - SVM scatter4 with scaling pitch](instructions/SVM_SCATTER4_SCALED.md)
 
-- [SVM_GATHER - SMV gather](instructions/SVM_GATHER.md)
+- [SVM_SCATTER - SMV scatter](instructions/SVM_SCATTER.md)
 
-- [SVM_BLOCK_ST - SMV Block Store](instructions/SVM_BLOCK_ST.md)
+- [SVM_ATOMIC - SVM atomic operations](instructions/SVM_ATOMIC.md)
 
 
 Synchronization Instructions

documentation/visa/7_appendix_debug_information.md

@@ -229,6 +229,8 @@ Debug information header format is as follows:
       VarLiveIntervalsGenISA callerbefp;
       ub retAddrValid;
       VarLiveIntervalsGenISA retAddr;
+      uw CEOffsetFromFPOff;
+      uw CEStoreIP;
       uw numCalleeSaveEntries;
       PhyRegSaveInfoPerIP calleeSaveEntry[numCalleeSaveEntries];
       ud numCallerSaveEntries;
@@ -250,6 +252,11 @@ Debug information header format is as follows:
     frame.
 -   **retAddr:** Live-interval of variable holding return address of
     current frame. Valid only if retAddrValid is 1.
+-   **CEOffsetFromFPOff:** Offset from FP where CE ARF register value
+    is stored in current frame. If the value is not stored then this
+    field is 0xffff.
+-   **CEStoreIP:** IP from where CE register value is available on
+    stack. Valid only when CEOffsetFromFPOff is not 0xffff.
 -   **numCalleeSaveEntries:** Number of entries in callee save area
     table. Useful during virtual stack unwinding.
 -   **calleeSaveEntry:** Caller frame's variables allocated to callee

documentation/visa/instructions/LSC_UNTYPED.md

@@ -329,19 +329,13 @@ and enables one to emulate block loads and stores.
 In this mode a single address is taken and loads successive vector components
 across a regster (or block of them).  Note, transpose only supports SIMD1.
 
-Kernel payload arguments can be read in a program using `AddrType` == `arg`.
-Here is spec defining implicit arguments that may be read using this
-`AddrType`:
-https://github.com/intel-innersource/drivers.gpu.abi/blob/master/internal/implicit-args.md
-
 Atomic operations (except for append counter atomic) are also gather/scatter
 operation.  They operate on the addresses in `Src0Addrs` and possibly with data
 in `Src1Data` and `Src2Data`, and can read back the result to `DstData`
 (or use `%null` to avoid the writeback).  For operations that do not use
 `Src1Data` or `Src2Data`, specify the null register `%null`.  Transpose is
 not permitted for atomic operations.
 
-
 The `lsc_load_strided` and `lsc_store_strided` operations take a single
 address and a stride and generate an arithmetic (linear) sequence to
 compute each SIMT address to load.  Similar to the `lsc_load`/`lsc_store`

documentation/visa/instructions/LZD.md

@@ -86,7 +86,6 @@ SPDX-License-Identifier: MIT
 
 #### Properties
 - **Supported Types:** UD
-- **Saturation:** Yes
 - **Source Modifier:** false
 
 

documentation/visa/instructions/SRND.md

@@ -95,10 +95,10 @@ SPDX-License-Identifier: MIT
 #### Operand type maps
 - **Type map**
   -  **Dst types:** HF
-  -  **Src types:** F
+  -  **Src types:**
 - **Type map**
   -  **Dst types:** UB
-  -  **Src types:** HF
+  -  **Src types:**
 
 
 ## Text