Fix SIMD16 shuffle down

Change-Id: I19d39ccd3049bfa73ee5469d98085f6a3fe425bd

Author: PiotrFusik

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -4818,9 +4818,10 @@ void EmitPass::emitSimdShuffleDown(llvm::Instruction* inst)
     m_encoder->Cast(pLaneId, imm0);
     m_encoder->Push();
 
-    if (m_SimdMode == SIMDMode::SIMD16)
+    if (m_SimdMode == SIMDMode::SIMD16 || m_SimdMode == SIMDMode::SIMD32)
     {
-        m_encoder->SetDstSubVar(1);
+        m_encoder->SetDstSubVar(0);
+        m_encoder->SetDstSubReg(8);
         m_encoder->SetSimdSize(SIMDMode::SIMD8);
         m_encoder->SetNoMask();
         CVariable* imm1 = m_currShader->ImmToVariable(0x8, ISA_TYPE_UD);
@@ -4830,18 +4831,10 @@ void EmitPass::emitSimdShuffleDown(llvm::Instruction* inst)
 
     if (m_SimdMode == SIMDMode::SIMD32)
     {
-        m_encoder->SetDstSubVar(0);
-        m_encoder->SetDstSubReg(8);
-        m_encoder->SetSimdSize(SIMDMode::SIMD8);
-        m_encoder->SetNoMask();
-        CVariable* imm1 = m_currShader->ImmToVariable(0x8, ISA_TYPE_UD);
-        m_encoder->Add(pLaneId, pLaneId, imm1);
-        m_encoder->Push();
-
         m_encoder->SetSimdSize(SIMDMode::SIMD16);
         m_encoder->SetDstSubReg(16);
         m_encoder->SetNoMask();
-        imm1 = m_currShader->ImmToVariable(0x10, ISA_TYPE_UD);
+        CVariable* imm1 = m_currShader->ImmToVariable(0x10, ISA_TYPE_UD);
         m_encoder->Add(pLaneId, pLaneId, imm1);
         m_encoder->Push();
     }

visa/HWConformity.cpp

@@ -1694,15 +1694,15 @@ bool HWConformity::fixIndirectOpnd( INST_LIST_ITER i, G4_BB *bb )
         addr_dcl0 = src0->asSrcRegRegion()->getBase()->asRegVar()->getDeclare()->getRootDeclare();
         // is the following precise?
         src0_count = addr_dcl0->getTotalElems();
-        MUST_BE_TRUE(src0_count <= addr_reg_max_count, "More than 8 address subregisters required for one oerand.");
+        MUST_BE_TRUE(src0_count <= addr_reg_max_count, "More than 8 address subregisters required for one operand.");
         src_uniq_count += src0_count;
     }
 
     if (!null_src1 && src1->isSrcRegRegion() &&
         src1->getRegAccess() != Direct && src1->asSrcRegRegion()->getBase()->isRegVar()) {
         addr_dcl1 = src1->asSrcRegRegion()->getBase()->asRegVar()->getDeclare()->getRootDeclare();
         src1_count = addr_dcl1->getTotalElems();
-        MUST_BE_TRUE(src1_count <= addr_reg_max_count, "More than 8 address subregisters required for one oerand.");
+        MUST_BE_TRUE(src1_count <= addr_reg_max_count, "More than 8 address subregisters required for one operand.");
         if (addr_dcl1 != addr_dcl0) {
             // should we use top level dcl here?
             src_uniq_count += src1_count;
@@ -1718,7 +1718,7 @@ bool HWConformity::fixIndirectOpnd( INST_LIST_ITER i, G4_BB *bb )
     {
         addr_dcl2 = dst->getBase()->asRegVar()->getDeclare()->getRootDeclare();
         dst_count = addr_dcl2->getTotalElems();
-        MUST_BE_TRUE(dst_count <= addr_reg_max_count, "More than 8 address subregisters required for one oerand.");
+        MUST_BE_TRUE(dst_count <= addr_reg_max_count, "More than 8 address subregisters required for one operand.");
         if (addr_dcl2 != addr_dcl0 && addr_dcl2 != addr_dcl1) {
             dst_uniq_count += dst_count;
         }