Add support for Panther Lake devices

.

Author: vsemenov368

IGC/VectorCompiler/cmake/supported_platforms_list.cmake

@@ -19,4 +19,5 @@ set(SUPPORTED_VC_PLATFORMS
     "XeHPC"
     "XeHPCVG"
     "Xe2"
+    "Xe3"
     )

IGC/VectorCompiler/igcdeps/src/TranslationInterface.cpp

@@ -177,6 +177,10 @@ getPlatformName(const PLATFORM &Platform) {
     if (Product == IGFX_BMG)
       return {"Xe2", RevId};
     break;
+  case IGFX_XE3_CORE:
+    if (Product == IGFX_PTL)
+      return {"Xe3", RevId};
+    LLVM_FALLTHROUGH;
   default:
     break;
   }

IGC/VectorCompiler/include/GenXSubtarget.h

@@ -62,6 +62,7 @@ class GenXSubtarget final : public GenXGenSubtargetInfo {
     XeHPC,
     XeHPCVG,
     Xe2,
+    Xe3,
     Invalid,
   };
 
@@ -225,6 +226,9 @@ class GenXSubtarget final : public GenXGenSubtargetInfo {
   /// True if subtarget supports large GRF mode
   bool HasLargeGRF = false;
 
+  /// True if subtarget supports VRT
+  bool HasVRT = false;
+
   // True if target supports local integer compare exchange 64-bit
   bool HasLocalIntegerCas64 = false;
 
@@ -423,6 +427,8 @@ class GenXSubtarget final : public GenXGenSubtargetInfo {
 
   bool hasLargeGRF() const { return HasLargeGRF; }
 
+  bool hasVRT() const { return HasVRT; }
+
   /// * getsHWTIDFromPredef - some subtargets get HWTID from
   // predefined variable instead of sr0, returns *true* for such ones.
   bool getsHWTIDFromPredef() const { return GetsHWTIDFromPredef; }

IGC/VectorCompiler/lib/Driver/Driver.cpp

@@ -798,7 +798,12 @@ static Error fillApiOptions(const opt::ArgList &ApiOptions,
   if (opt::Arg *A = ApiOptions.getLastArg(OPT_exp_register_file_size_common)) {
     StringRef V = A->getValue();
     auto MaybeGRFSize = StringSwitch<llvm::Optional<unsigned>>(V)
+                            .Case("32", 32)
+                            .Case("64", 64)
+                            .Case("96", 96)
                             .Case("128", 128)
+                            .Case("160", 160)
+                            .Case("192", 192)
                             .Case("256", 256)
                             .Default({});
     if (!MaybeGRFSize)

IGC/VectorCompiler/lib/GenXCodeGen/GenX.td

@@ -237,6 +237,12 @@ def FeatureHasMediaWalker : SubtargetFeature<"feature_has_media_walker",
 def FeatureHasLargeGRF : SubtargetFeature<"feature_has_large_grf",
                                           "HasLargeGRF", "true",
                                           "Target supports large GRF mode">;
+def FeatureHasVRT : SubtargetFeature<"feature_has_variable_regs_per_thread",
+                                     "HasVRT", "true",
+                                     "Target supports variable amount of registers per thread">;
+def FeatureHas10ThreadsPerEU : SubtargetFeature<"feature_10threads_per_eu",
+                                                "NumThreadsPerEU", "10",
+                                                "Target has 10 threads per EU">;
 def FeatureHas7ThreadsPerEU : SubtargetFeature<"feature_7threads_per_eu",
                                                 "NumThreadsPerEU", "7",
                                                 "Target has 7 threads per EU">;
@@ -525,6 +531,39 @@ def : Proc<"Xe2", [
   FeatureTransLegacy,
 ]>;
 
+def : Proc<"Xe3", [
+  FeatureFP64,
+  FeatureGRFByteSize64,
+  FeatureHas10ThreadsPerEU,
+  FeatureHasAdd3,
+  FeatureHasBfn,
+  FeatureHasLSC,
+  FeatureHasLSCOffset,
+  FeatureHasLSCTyped,
+  FeatureHasLargeGRF,
+  FeatureHasMadSimd32,
+  FeatureHasNamedBarriers,
+  FeatureHasOWordSLM,
+  FeatureHasSampler,
+  FeatureHasVRT,
+  FeatureIEEEDivSqrt,
+  FeatureIndirectGRFCrossing,
+  FeatureInstr64BitRotate,
+  FeatureInstrAdd64,
+  FeatureInstrGlobalAtomicAddF64,
+  FeatureInstrLocalIntegerCas64,
+  FeatureLSCMaxWidth32,
+  FeatureLongLong,
+  FeatureNoLegacyDataport,
+  FeaturePartialI64Emulation,
+  FeaturePreemption,
+  FeatureSLM128K,
+  FeatureSwitchjmp,
+  FeatureSystolicDenormControl,
+  FeatureThreadPayloadInMemory,
+  FeatureTransLegacy,
+]>;
+
 def GenX : Target {
   // Nothing here (yet?)
 }

IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.cpp

@@ -70,6 +70,7 @@ void GenXSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
                  .Case("XeHPC", XeHPC)
                  .Case("XeHPCVG", XeHPCVG)
                  .Case("Xe2", Xe2)
+                 .Case("Xe3", Xe3)
                  .Default(Invalid);
 
   std::string CPUName(CPU);
@@ -103,6 +104,8 @@ uint32_t GenXSubtarget::getMaxThreadsNumPerSubDevice() const {
     return 1 << 12;
   case Xe2:
     return 1 << 13;
+  case Xe3:
+    return 1 << 15;
   }
   return 0;
 }
@@ -148,6 +151,16 @@ ArrayRef<std::pair<int, int>> GenXSubtarget::getThreadIdReservedBits() const {
     static const std::pair<int, int> Bits[] = {{10, 1}, {7, 1}, {3, 1}};
     return Bits;
   }
+  case GenXSubtarget::Xe3: {
+    // [17:14] Slice ID.
+    // [13:12] : Reserved MBZ
+    // [11:8] SubSlice ID
+    // [7] : Reserved MBZ
+    // [6:4] : EUID
+    // [3:0] : TID
+    static const std::pair<int, int> Bits[] = {{12, 2}, {7, 1}};
+    return Bits;
+  }
   default:
     // All other platforms have pre-defined Thread ID register
     return {};
@@ -205,7 +218,8 @@ ArrayRef<std::pair<int, int>> GenXSubtarget::getEUIdBits() const {
     static const std::pair<int, int> Bits[] = {{4, 2}, {8, 1}};
     return Bits;
   }
-  case GenXSubtarget::Xe2: {
+  case GenXSubtarget::Xe2:
+  case GenXSubtarget::Xe3: {
     // [6:4] : EUID
     static const std::pair<int, int> Bits[] = {{4, 3}};
     return Bits;
@@ -218,6 +232,11 @@ ArrayRef<std::pair<int, int>> GenXSubtarget::getEUIdBits() const {
 
 ArrayRef<std::pair<int, int>> GenXSubtarget::getThreadIdBits() const {
   switch (TargetId) {
+  case GenXSubtarget::Xe3: {
+    // [3:0] : EUID
+    static const std::pair<int, int> Bits[] = {{0, 4}};
+    return Bits;
+  }
   default:
     static const std::pair<int, int> Bits[] = {{0, 3}};
     return Bits;
@@ -252,6 +271,8 @@ TARGET_PLATFORM GenXSubtarget::getVisaPlatform() const {
     return TARGET_PLATFORM::Xe_PVCXT;
   case Xe2:
     return TARGET_PLATFORM::Xe2;
+  case Xe3:
+    return TARGET_PLATFORM::Xe3;
   default:
     return TARGET_PLATFORM::GENX_NONE;
   }
@@ -287,6 +308,11 @@ bool GenXSubtarget::isValidGRFSize(unsigned Size) const {
   case GenXSubtarget::XeHPCVG:
   case GenXSubtarget::Xe2:
     return Size == 128 || Size == 256;
+  case GenXSubtarget::Xe3: {
+    static const std::unordered_set<unsigned> Supported = {32,  64,  96, 128,
+                                                           160, 192, 256};
+    return Supported.count(Size);
+  }
   default:
     return Size == 128; // platforms <= TGL
   }

IGC/VectorCompiler/lib/GenXCodeGen/Utils/cisa_gen_intrinsics.json

@@ -3652,6 +3652,20 @@
       "opc": "ISA_SBARRIER",
       "signal_flag": [ "BYTE", 1 ]
     },
+    "genx_qf_cvt": {
+      "opc": "ISA_FCVT",
+      "exec_size": [ "EXECSIZE_NOMASK" ],
+      "elementwise": [ "ELEMENTWISE" ],
+      "dst": [ "GENERAL", "UNSIGNED", "SATURATION_INTALLOWED", 0 ],
+      "src0": [ "GENERAL", "UNSIGNED", "NOIMM", 1 ]
+    },
+    "genx_hf8_cvt": {
+      "opc": "ISA_FCVT",
+      "exec_size": [ "EXECSIZE_NOMASK" ],
+      "elementwise": [ "ELEMENTWISE" ],
+      "dst": [ "GENERAL", "SIGNED", "SATURATION_INTALLOWED", 0 ],
+      "src0": [ "GENERAL", "SIGNED", "NOIMM", 1 ]
+    },
     "genx_bfrev": {
       "opc": "ISA_BFREV",
       "exec_size": [ "EXECSIZE" ],

IGC/VectorCompiler/test/CisaBuilder/bf8_cvt_in.ll

@@ -0,0 +1,59 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2021-2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; COM: ;;;;;;;;;; RUNNERS ;;;;;;;;;;
+
+; RUN: %llc_typed_ptrs %s -march=genx64 -mcpu=Xe3 -vc-skip-ocl-runtime-info -finalizer-opts='-dumpcommonisa -isaasmToConsole' -o /dev/null \
+; RUN: | FileCheck %s
+; RUN: %llc_opaque_ptrs %s -march=genx64 -mcpu=Xe3 -vc-skip-ocl-runtime-info -finalizer-opts='-dumpcommonisa -isaasmToConsole' -o /dev/null \
+; RUN: | FileCheck %s
+
+; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;
+
+; CHECK-DAG: .decl [[SRC:V[^ ]+]] v_type=G type=ub num_elts=16 alias
+; CHECK-DAG: .decl [[DST:V[^ ]+]] v_type=G type=hf num_elts=16 alias
+; CHECK: fcvt (M1_NM, 16) [[DST]](0,0)<1> [[SRC]](0,0)<1;1,0>
+
+
+
+; COM: ;;;;;;;;;; KERNEL ;;;;;;;;;;
+
+target datalayout = "e-p:64:64-i64:64-n8:16:32"
+target triple = "genx64-unknown-unknown"
+
+declare <16 x i8> @llvm.genx.oword.ld.v16i8(i32, i32, i32)
+declare <16 x half> @llvm.genx.qf.cvt.v16f16.v16i8(<16 x i8>)
+declare void @llvm.genx.oword.st.v16f16(i32, i32, <16 x half>)
+
+define dllexport spir_kernel void @bf8_cvtKernel_in(i32 %0, i32 %1) local_unnamed_addr #0 {
+  %vec = tail call <16 x i8> @llvm.genx.oword.ld.v16i8(i32 0, i32 %0, i32 0)
+  %upd_vec = tail call <16 x half> @llvm.genx.qf.cvt.v16f16.v16i8(<16 x i8> %vec)
+  tail call void @llvm.genx.oword.st.v16f16(i32 %1, i32 0, <16 x half> %upd_vec)
+  ret void
+}
+
+attributes #0 = { noinline nounwind "CMGenxMain" }
+
+!spirv.Source = !{!1}
+!opencl.spir.version = !{!2}
+!opencl.ocl.version = !{!1}
+!opencl.used.extensions = !{!0}
+!opencl.used.optional.core.features = !{!0}
+!spirv.Generator = !{!3}
+!genx.kernels = !{!4}
+!genx.kernel.internal = !{!8}
+
+!0 = !{}
+!1 = !{i32 0, i32 0}
+!2 = !{i32 1, i32 2}
+!3 = !{i16 6, i16 14}
+!4 = !{void (i32, i32)* @bf8_cvtKernel_in, !"bf8_cvtKernel_in", !5, i32 0, !6, !1, !7, i32 0}
+!5 = !{i32 2, i32 2}
+!6 = !{i32 64, i32 68}
+!7 = !{!"buffer_t", !"buffer_t"}
+!8 = !{void (i32, i32)* @bf8_cvtKernel_in, null, null, null, null}

IGC/VectorCompiler/test/CisaBuilder/bf8_cvt_in_sat.ll

@@ -0,0 +1,62 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2021-2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; COM: ;;;;;;;;;; RUNNERS ;;;;;;;;;;
+
+; RUN: %llc_typed_ptrs %s -march=genx64 -mcpu=Xe3 -vc-skip-ocl-runtime-info -finalizer-opts='-dumpcommonisa -isaasmToConsole' -o /dev/null \
+; RUN: | FileCheck %s
+; RUN: %llc_opaque_ptrs %s -march=genx64 -mcpu=Xe3 -vc-skip-ocl-runtime-info -finalizer-opts='-dumpcommonisa -isaasmToConsole' -o /dev/null \
+; RUN: | FileCheck %s
+
+; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;
+
+; CHECK-DAG: .decl [[SRC:V[^ ]+]] v_type=G type=ub num_elts=16 alias
+; CHECK-DAG: .decl [[DST:V[^ ]+]] v_type=G type=hf num_elts=16 alias
+; CHECK: fcvt (M1_NM, 16) [[DST]](0,0)<1> [[SRC]](0,0)<1;1,0>
+; CHECK-NEXT: mov.sat (M1, 16) [[SAT:V[0-9]+]](0,0)<1>
+
+
+
+; COM: ;;;;;;;;;; KERNEL ;;;;;;;;;;
+
+target datalayout = "e-p:64:64-i64:64-n8:16:32"
+target triple = "genx64-unknown-unknown"
+
+declare <16 x i8> @llvm.genx.oword.ld.v16i8(i32, i32, i32)
+declare <16 x half> @llvm.genx.qf.cvt.v16f16.v16i8(<16 x i8>)
+declare <16 x half> @llvm.genx.sat.v16f16(<16 x half>)
+declare void @llvm.genx.oword.st.v16f16(i32, i32, <16 x half>)
+
+define dllexport spir_kernel void @bf8_cvtKernel_in_sat(i32 %0, i32 %1) local_unnamed_addr #0 {
+  %vec = tail call <16 x i8> @llvm.genx.oword.ld.v16i8(i32 0, i32 %0, i32 0)
+  %upd_vec = tail call <16 x half> @llvm.genx.qf.cvt.v16f16.v16i8(<16 x i8> %vec)
+  %sat = tail call <16 x half> @llvm.genx.sat.v16f16(<16 x half> %upd_vec)
+  tail call void @llvm.genx.oword.st.v16f16(i32 %1, i32 0, <16 x half> %sat)
+  ret void
+}
+
+attributes #0 = { noinline nounwind "CMGenxMain" }
+
+!spirv.Source = !{!1}
+!opencl.spir.version = !{!2}
+!opencl.ocl.version = !{!1}
+!opencl.used.extensions = !{!0}
+!opencl.used.optional.core.features = !{!0}
+!spirv.Generator = !{!3}
+!genx.kernels = !{!4}
+!genx.kernel.internal = !{!8}
+
+!0 = !{}
+!1 = !{i32 0, i32 0}
+!2 = !{i32 1, i32 2}
+!3 = !{i16 6, i16 14}
+!4 = !{void (i32, i32)* @bf8_cvtKernel_in_sat, !"bf8_cvtKernel_in_sat", !5, i32 0, !6, !1, !7, i32 0}
+!5 = !{i32 2, i32 2}
+!6 = !{i32 64, i32 68}
+!7 = !{!"buffer_t", !"buffer_t"}
+!8 = !{void (i32, i32)* @bf8_cvtKernel_in_sat, null, null, null, null}

IGC/VectorCompiler/test/CisaBuilder/bf8_cvt_out.ll

@@ -0,0 +1,60 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2021-2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; COM: ;;;;;;;;;; RUNNERS ;;;;;;;;;;
+
+; RUN: %llc_typed_ptrs %s -march=genx64 -mcpu=Xe3 -vc-skip-ocl-runtime-info -finalizer-opts='-dumpcommonisa -isaasmToConsole' -o /dev/null \
+; RUN: | FileCheck %s
+; RUN: %llc_opaque_ptrs %s -march=genx64 -mcpu=Xe3 -vc-skip-ocl-runtime-info -finalizer-opts='-dumpcommonisa -isaasmToConsole' -o /dev/null \
+; RUN: | FileCheck %s
+
+
+; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;
+
+; CHECK-DAG: .decl [[SRC:V[^ ]+]] v_type=G type=hf num_elts=16 alias
+; CHECK-DAG: .decl [[DST:V[^ ]+]] v_type=G type=ub num_elts=16 alias
+; CHECK: fcvt (M1_NM, 16) [[DST]](0,0)<1> [[SRC]](0,0)<1;1,0>
+
+
+
+; COM: ;;;;;;;;;; KERNEL ;;;;;;;;;;
+
+target datalayout = "e-p:64:64-i64:64-n8:16:32"
+target triple = "genx64-unknown-unknown"
+
+declare <16 x half> @llvm.genx.oword.ld.v16f16(i32, i32, i32)
+declare <16 x i8> @llvm.genx.qf.cvt.v16i8.v16f16(<16 x half>)
+declare void @llvm.genx.oword.st.v16i8(i32, i32, <16 x i8>)
+
+define dllexport spir_kernel void @bf8_cvtKernel_out(i32 %0, i32 %1) local_unnamed_addr #0 {
+  %vec = tail call <16 x half> @llvm.genx.oword.ld.v16f16(i32 0, i32 %0, i32 0)
+  %upd_vec = tail call <16 x i8> @llvm.genx.qf.cvt.v16i8.v16f16(<16 x half> %vec)
+  tail call void @llvm.genx.oword.st.v16i8(i32 %1, i32 0, <16 x i8> %upd_vec)
+  ret void
+}
+
+attributes #0 = { noinline nounwind "CMGenxMain" }
+
+!spirv.Source = !{!1}
+!opencl.spir.version = !{!2}
+!opencl.ocl.version = !{!1}
+!opencl.used.extensions = !{!0}
+!opencl.used.optional.core.features = !{!0}
+!spirv.Generator = !{!3}
+!genx.kernels = !{!4}
+!genx.kernel.internal = !{!8}
+
+!0 = !{}
+!1 = !{i32 0, i32 0}
+!2 = !{i32 1, i32 2}
+!3 = !{i16 6, i16 14}
+!4 = !{void (i32, i32)* @bf8_cvtKernel_out, !"bf8_cvtKernel_out", !5, i32 0, !6, !1, !7, i32 0}
+!5 = !{i32 2, i32 2}
+!6 = !{i32 64, i32 68}
+!7 = !{!"buffer_t", !"buffer_t"}
+!8 = !{void (i32, i32)* @bf8_cvtKernel_out, null, null, null, null}