Legalize vector fneg instructions

IGC's legalization phase was not able to properly legalize `fneg` instructions
that operate on a vector type. This issue has been exposed while merging
commit f8f17a0 which has disabled scalarization
of vector `fneg` instructions in `ScalarizeFunction` pass for `optnone` functions.

`ScalarizeFunction` pass is not intented to be a legalization pass. It's rather
treated as an optimization pass, so whatever gets disabled in its implementation,
shouldn't affect the final kernel correctness.

`ScalarizerCodeGen` pass is a pass that runs during legalization phase and it's
specifically designed to scalarize instructions that cannot be properly handled
by `EmitVISAPass` if they are in a vector form. This change extends the
capabilities of `ScalarizerCodeGen`, so that it can properly scalarize `fneg`
vector instructions.

This change also fixes a bug introduced in f8f17a0
which sometimes resulted in creating fneg instruction with `undef`` values.

Author: aratajew

IGC/Compiler/CISACodeGen/ScalarizerCodeGen.cpp

@@ -152,3 +152,29 @@ void ScalarizerCodeGen::visitCastInst(llvm::CastInst& I)
         }
     }
 }
+
+#if LLVM_VERSION_MAJOR >= 10
+void ScalarizerCodeGen::visitFNeg(llvm::UnaryOperator& I)
+{
+    if (I.getType()->isVectorTy())
+    {
+        IGCLLVM::FixedVectorType* InstType = cast<IGCLLVM::FixedVectorType>(I.getType());
+        unsigned NumElements = int_cast<unsigned>(InstType->getNumElements());
+        Value* Src = I.getOperand(0);
+        m_builder->SetInsertPoint(&I);
+
+        Value* LastOp = UndefValue::get(InstType);
+        for (unsigned Idx = 0; Idx < NumElements; Idx++)
+        {
+            Value* ConstIndex = ConstantInt::get(m_builder->getInt32Ty(), Idx);
+            Value* EESrc0 = m_builder->CreateExtractElement(Src, ConstIndex);
+            Value* NewFNegInst = m_builder->CreateFNeg(EESrc0);
+            LastOp = m_builder->CreateInsertElement(LastOp, NewFNegInst, ConstIndex);
+        }
+
+        // Now replace all the instruction users with the newly created instruction
+        I.replaceAllUsesWith(LastOp);
+        I.eraseFromParent();
+    }
+}
+#endif

IGC/Compiler/CISACodeGen/ScalarizerCodeGen.hpp

@@ -31,6 +31,9 @@ namespace IGC
         virtual bool runOnFunction(llvm::Function& F);
         void visitBinaryOperator(llvm::BinaryOperator& I);
         void visitCastInst(llvm::CastInst& I);
+#if LLVM_VERSION_MAJOR >= 10
+        void visitFNeg(llvm::UnaryOperator& I);
+#endif
 
     private:
         llvm::IRBuilder<>* m_builder = nullptr;

IGC/Compiler/Optimizer/Scalarizer.cpp

@@ -426,7 +426,7 @@ void ScalarizeFunction::scalarizeInstruction(UnaryOperator* UI)
     IGCLLVM::FixedVectorType* instType = dyn_cast<IGCLLVM::FixedVectorType>(UI->getType());
     // Do not apply if optnone function
     if (UI->getFunction()->hasOptNone())
-        return;
+        return recoverNonScalarizableInst(UI);
 
     // Only need handling for vector binary ops
     if (!instType) return;

IGC/Compiler/tests/ScalarizeFunction/fneg_optnone.ll

@@ -0,0 +1,35 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+;
+; REQUIRES: llvm-14-plus
+; RUN: igc_opt %s -S -o - --igc-scalarize | FileCheck %s
+
+; Function Attrs: noinline optnone
+define void @test_fneg_optnone(<4 x float> %src, <3 x float> addrspace(1)* %out) #0 {
+
+; CHECK-LABEL: @test_fneg_optnone(
+;
+; CHECK: [[EE0:%.*]] = extractelement <4 x float> %src, i32 0
+; CHECK: [[EE1:%.*]] = extractelement <4 x float> %src, i32 1
+; CHECK: [[EE2:%.*]] = extractelement <4 x float> %src, i32 2
+; CHECK: [[EE3:%.*]] = extractelement <4 x float> %src, i32 3
+; CHECK: [[IE0:%.*]] = insertelement <3 x float> undef, float [[EE0]], i32 0
+; CHECK: [[IE1:%.*]] = insertelement <3 x float> [[IE0]], float [[EE1]], i32 1
+; CHECK: [[IE2:%.*]] = insertelement <3 x float> [[IE1]], float [[EE2]], i32 2
+; CHECK: [[FNEG:%.*]] = fneg <3 x float> [[IE2]]
+; CHECK: store <3 x float> [[FNEG]], <3 x float> addrspace(1)* %out, align 4
+
+; CHECK-NOT: fneg <3 x float> undef
+
+  %1 = shufflevector <4 x float> %src, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %2 = fneg <3 x float> %1
+  store <3 x float> %2, <3 x float> addrspace(1)* %out, align 4
+  ret void
+}
+
+attributes #0 = { noinline optnone }

IGC/Compiler/tests/ScalarizerCodeGen/fneg.ll

@@ -0,0 +1,33 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+;
+; REQUIRES: llvm-14-plus
+; RUN: igc_opt %s -S -o - --igc-scalarizer-in-codegen | FileCheck %s
+; ------------------------------------------------
+; ScalarizerCodeGen
+; ------------------------------------------------
+
+define void @test_fneg_scalarization(<3 x float> %src, <3 x float> addrspace(1)* %out) {
+
+; CHECK-LABEL: @test_fneg_scalarization(
+;
+; CHECK: [[EE0:%.*]] = extractelement <3 x float> %src, i32 0
+; CHECK: [[FNEG0:%.*]] = fneg float [[EE0]]
+; CHECK: [[IE0:%.*]] = insertelement <3 x float> undef, float [[FNEG0]], i32 0
+; CHECK: [[EE1:%.*]] = extractelement <3 x float> %src, i32 1
+; CHECK: [[FNEG1:%.*]] = fneg float [[EE1]]
+; CHECK: [[IE1:%.*]] = insertelement <3 x float> [[IE0]], float [[FNEG1]], i32 1
+; CHECK: [[EE2:%.*]] = extractelement <3 x float> %src, i32 2
+; CHECK: [[FNEG2:%.*]] = fneg float [[EE2]]
+; CHECK: [[IE2:%.*]] = insertelement <3 x float> [[IE1]], float [[FNEG2]], i32 2
+; CHECK: store <3 x float> [[IE2]], <3 x float> addrspace(1)* %out, align 4
+
+  %1 = fneg <3 x float> %src
+  store <3 x float> %1, <3 x float> addrspace(1)* %out, align 4
+  ret void
+}