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[Autobackout][FunctionalRegression]Revert of change: 7e2552b: Add PTL support
Add PTL support
1 parent ee57323 commit fbcc75b

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‎IGC/AdaptorCommon/API/igc.h‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -206,20 +206,5 @@ typedef enum
206206
FCEXP_DISABLED = FCEXP_TOBE_DESIGNED
207207
} FCEXP_FLAG_t;
208208

209-
//////////////////////////////////////////////////////////////////////////
210-
/// @brief Structure for passing precompiled LLVM bytecode to IGC.
211-
namespace IGC
212-
{
213-
struct BIFModule
214-
{
215-
uint64_t m_ByteCodeSize = 0;
216-
const void* m_pLLVMBytecode = nullptr;
217-
218-
// These bits are opaque to the IGC.
219-
// They can be used to provide configuration data for
220-
// the function(s) in the LLVM from the bytecode.
221-
uint64_t m_ConfigBits = 0;
222-
};
223-
}
224209
#endif // __IGC_H
225210

‎IGC/AdaptorCommon/RayTracing/API/BVHInfo.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,11 +21,9 @@ namespace IGC
2121
bool hasFixedOffset = false;
2222
size_t offset = 0;
2323

24-
bool uses64Bit = false;
2524
inline bool operator==(const BVHInfo& RHS) const
2625
{
2726
return (
28-
uses64Bit == RHS.uses64Bit &&
2927
hasFixedOffset == RHS.hasFixedOffset &&
3028
offset == RHS.offset
3129
);

‎IGC/AdaptorCommon/RayTracing/API/RayDispatchGlobalData.h‎

Lines changed: 0 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -232,65 +232,11 @@ struct RayDispatchGlobalData
232232
uint32_t bvhLevels : 3;
233233
uint32_t MBZ3 : 29;
234234
} rt_data_info;
235-
// In addition to the dword of padding to align `common`, we also
236-
// add 8 dwords so Xe and Xe3 both have the same RTGlobals size.
237235
uint32_t paddingBits[1+6]; // padding
238236

239237
// HW doesn't read anything below this point.
240238
RayDispatchGlobalDataCommon common;
241239
} xe;
242-
struct Xe3
243-
{
244-
template<class TAPIAdaptor>
245-
void populate(const TAPIAdaptor& umd)
246-
{
247-
rtMemBasePtr = umd.GetRayStackBufferAddress();
248-
callStackHandlerPtr = umd.GetCallStackHandlerPtr();
249-
stack_size_info.stackSizePerRay = umd.GetStackSizePerRay();
250-
num_stacks_info.numRTStacks = umd.GetNumDSSRTStacks();
251-
252-
// _pad1_mbz higher 16 bits must be zero.
253-
num_stacks_info.numRTStacks = (num_stacks_info.numRTStacks & 0x0000FFFF);
254-
255-
constexpr uint32_t strideMask = (1 << 13) - 1;
256-
const uint32_t hgs = umd.GetHitGroupStride() & strideMask;
257-
const uint32_t mss = umd.GetMissStride() & strideMask;
258-
rt_data_info.packedData = (umd.GetMaxBVHLevels() << 0) | (hgs << 3) | (mss << 16);
259-
260-
hitGroupBasePtr = umd.GetHitGroupTable();
261-
missShaderBasePtr = umd.GetMissShaderTable();
262-
263-
common.populate(umd);
264-
}
265-
266-
uint64_t rtMemBasePtr; // base address of the allocated stack memory
267-
uint64_t callStackHandlerPtr; // this is the KSP of the continuation handler that is invoked by BTD when the read KSP is 0
268-
union {
269-
uint32_t stackSizePerRay; // async-RT stack size in 64 byte blocks
270-
uint32_t _pad0_mbz : 32;
271-
} stack_size_info;
272-
union {
273-
uint32_t numRTStacks; // number of stacks per DSS
274-
uint32_t numDSSRTStacks : 16; // number of asynch stacks per DSS
275-
uint32_t _pad1_mbz : 16;
276-
277-
} num_stacks_info;
278-
union {
279-
uint32_t packedData;
280-
uint32_t maxBVHLevels : 3; // the maximal number of supported instancing levels (0->8, 1->1, 2->2, ...)
281-
uint32_t hitGroupStride : 13; // stride of hit group shader records (16-bytes alignment)
282-
uint32_t missShaderStride : 13; // stride of miss shader records (8-bytes alignment)
283-
uint32_t _pad2_mbz : 3;
284-
} rt_data_info;
285-
uint32_t flags : 1; // per context control flags
286-
uint32_t pad_mbz : 31;
287-
uint64_t hitGroupBasePtr; // base pointer of hit group shader record array (16-bytes alignment)
288-
uint64_t missShaderBasePtr; // base pointer of miss shader record array (8-bytes alignment)
289-
uint32_t _align_mbz[2]; // pad hardware section to 64 bytes
290-
291-
// HW doesn't read anything below this point.
292-
RayDispatchGlobalDataCommon common;
293-
} xe3;
294240
} rt;
295241
};
296242

@@ -305,8 +251,6 @@ static_assert(RTStackAlign % RayDispatchGlobalData::StackChunkSize == 0, "no?");
305251

306252
static_assert(sizeof(RayDispatchGlobalData) == 184, "unexpected size?");
307253
static_assert(sizeof(RayDispatchGlobalData::RT::Xe) == sizeof(RayDispatchGlobalData), "unexpected size?");
308-
static_assert(sizeof(RayDispatchGlobalData::RT::Xe3) == sizeof(RayDispatchGlobalData), "unexpected size?");
309-
static_assert(offsetof(RayDispatchGlobalData::RT::Xe, common) == offsetof(RayDispatchGlobalData::RT::Xe3, common), "unexpected size?");
310254
#ifdef HAS_INCLUDE_TYPE_TRAITS
311255
static_assert(std::is_standard_layout<RayDispatchGlobalData>::value, "no?");
312256
#endif // HAS_INCLUDE_TYPE_TRAITS

‎IGC/AdaptorCommon/RayTracing/AutoGenRTStackAccessPrivateOS.h‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -900,16 +900,6 @@ auto* _get_numDSSRTStacks_Xe(const Twine& _ReturnName = "")
900900
return V_2;
901901
}
902902

903-
auto* _get_maxBVHLevels_Xe3(const Twine& _ReturnName = "")
904-
{
905-
auto* V_0 = getGlobalBufferPtr();
906-
auto* V_1 = CreateInBoundsGEP(_struct_IGC__RayDispatchGlobalData(*Ctx.getModule()), V_0, { getInt64(0), getInt32(0), getInt32(0), getInt32(4), getInt32(0) });
907-
auto* V_2 = CreateLoad(getInt32Ty(), V_1);
908-
setInvariantLoad(V_2);
909-
auto* V_3 = CreateAnd(V_2, getInt32(7), _ReturnName);
910-
return V_3;
911-
}
912-
913903
auto* _get_statelessScratchPtr(const Twine& _ReturnName = "")
914904
{
915905
auto* V_0 = getGlobalBufferPtr();

‎IGC/AdaptorCommon/RayTracing/RTBuilder.cpp‎

Lines changed: 1 addition & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@ SPDX-License-Identifier: MIT
3636

3737

3838

39+
3940
using namespace llvm;
4041
using namespace RTStackFormat;
4142
using namespace IGC;
@@ -90,15 +91,6 @@ void RTBuilder::setInvariantLoad(LoadInst* LI)
9091

9192
Value* RTBuilder::getRtMemBasePtr(void)
9293
{
93-
#define STYLE(X) { \
94-
using T = std::conditional_t< \
95-
std::is_same_v<RTStackFormat::X, RTStackFormat::Xe>, \
96-
RayDispatchGlobalData::RT::Xe, RayDispatchGlobalData::RT::Xe3>; \
97-
static_assert( \
98-
offsetof(RayDispatchGlobalData::RT::Xe, rtMemBasePtr) == \
99-
offsetof(T, rtMemBasePtr)); }
100-
#include "RayTracingMemoryStyle.h"
101-
#undef STYLE
10294
return _get_rtMemBasePtr_Xe(VALUE_NAME("rtMemBasePtr"));
10395
}
10496

@@ -1178,10 +1170,6 @@ std::pair<uint32_t, uint32_t> RTBuilder::getSliceIDBitsInSR0() const {
11781170
{
11791171
return {11, 15};
11801172
}
1181-
else if (Ctx.platform.GetPlatformFamily() == IGFX_XE3_CORE)
1182-
{
1183-
return {14, 17};
1184-
}
11851173
else
11861174
{
11871175
return {12, 14};
@@ -1198,10 +1186,6 @@ std::pair<uint32_t, uint32_t> RTBuilder::getSubsliceIDBitsInSR0() const {
11981186
{
11991187
return {8, 9};
12001188
}
1201-
else if (Ctx.platform.GetPlatformFamily() == IGFX_XE3_CORE)
1202-
{
1203-
return {8, 11};
1204-
}
12051189
else
12061190
{
12071191
return {8, 8};
@@ -1252,13 +1236,6 @@ Value* RTBuilder::getGlobalDSSID()
12521236
{
12531237
return emitStateRegID(dssIDBits.first, sliceIDBits.second);
12541238
}
1255-
else if (isChildOfXe3)
1256-
{
1257-
Value* sliceID = emitStateRegID(sliceIDBits.first, sliceIDBits.second);
1258-
Value* dssID = emitStateRegID(dssIDBits.first, dssIDBits.second);
1259-
Value* globalDSSID = CreateMul(sliceID, getInt32(NumDSSPerSlice));
1260-
return CreateAdd(globalDSSID, dssID);
1261-
}
12621239
else
12631240
{
12641241
Value* dssID = emitStateRegID(dssIDBits.first, dssIDBits.second);

‎IGC/AdaptorCommon/RayTracing/RTBuilder.h‎

Lines changed: 0 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,6 @@ class RTBuilder : public IGCIRBuilder<>
5959

6060

6161
bool isChildOfXe2 = false;
62-
bool isChildOfXe3 = false;
6362

6463
// Field for explicit GlobalBufferPtr - used on OpenCL path.
6564
Value* GlobalBufferPtr = nullptr;
@@ -76,36 +75,8 @@ class RTBuilder : public IGCIRBuilder<>
7675
enabledSlices++;
7776
}
7877
}
79-
isChildOfXe3 = Ctx.platform.isCoreChildOf(IGFX_XE3_CORE);
8078
isChildOfXe2 = Ctx.platform.isCoreChildOf(IGFX_XE2_HPG_CORE);
8179

82-
if (isChildOfXe3)
83-
{
84-
EuCountPerDSS = SysInfo.MaxEuPerSubSlice;
85-
MaxDualSubSlicesSupported = 0;
86-
87-
IGC_ASSERT(NumDSSPerSlice <= GT_MAX_SUBSLICE_PER_SLICE);
88-
89-
for (unsigned int sliceID = 0; sliceID < GT_MAX_SLICE; ++sliceID)
90-
{
91-
if (SysInfo.SliceInfo[sliceID].Enabled)
92-
{
93-
NumDSSPerSlice = SysInfo.SliceInfo[sliceID].SubSliceEnabledCount;
94-
95-
// SubSliceInfo size is GT_MAX_SUBSLICE_PER_SLICE, but
96-
// actual number, calculated for given platform, of SubSlices is used
97-
// to iterate only through SubSlices present on the platform.
98-
for (unsigned int ssID = 0; ssID < NumDSSPerSlice; ++ssID)
99-
{
100-
if (SysInfo.SliceInfo[sliceID].SubSliceInfo[ssID].Enabled)
101-
{
102-
MaxDualSubSlicesSupported = std::max(MaxDualSubSlicesSupported, (sliceID * NumDSSPerSlice) + ssID + 1);
103-
}
104-
}
105-
}
106-
}
107-
}
108-
else // this will chain into if from Xe2 branch forming else if
10980
if (isChildOfXe2 || Ctx.platform.isProductChildOf(IGFX_PVC))
11081
{
11182
NumDSSPerSlice = SysInfo.MaxSubSlicesSupported / std::max(SysInfo.MaxSlicesSupported, enabledSlices);
@@ -283,8 +254,6 @@ class RTBuilder : public IGCIRBuilder<>
283254
Value* getStatelessScratchPtr(void);
284255
Value* getLeafType(StackPointerVal* StackPointer, bool CommittedHit);
285256
Value* getIsFrontFace(StackPointerVal* StackPointer, IGC::CallableShaderTypeMD ShaderTy);
286-
// Xe3: memhit->leafNodeSubType
287-
Value* getLeafNodeSubType(StackPointerVal* StackPointer, bool CommittedHit);
288257

289258
Value* CreateSyncStackPtrIntrinsic(Value* Addr, Type* PtrTy, bool AddDecoration);
290259

‎IGC/BiFModule/Headers/bif_flag_controls.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,5 +36,4 @@ BIF_FLAG_CONTROL(bool, UseHighAccuracyMath)
3636
BIF_FLAG_CONTROL(bool, EnableSWSrgbWrites)
3737
BIF_FLAG_CONTROL(int, MaxHWThreadIDPerSubDevice)
3838
BIF_FLAG_CONTROL(int, JointMatrixLoadStoreOpt)
39-
BIF_FLAG_CONTROL(bool, UseOOBChecks)
4039
#endif // __BIF_FLAG_CONTROL_H__

‎IGC/BiFModule/Implementation/group.cl‎

Lines changed: 0 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -2229,10 +2229,6 @@ short SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformBroadcast, _i32_i16_i32, )
22292229
{
22302230
if (Execution == Subgroup)
22312231
{
2232-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
2233-
{
2234-
Id = Id & (get_max_sub_group_size() - 1);
2235-
}
22362232
return as_ushort(__builtin_IB_simd_shuffle_h(as_half(Value), Id));
22372233
}
22382234
else
@@ -2296,10 +2292,6 @@ double SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformBroadcast, _i32_f64_i32,
22962292
{
22972293
if (Execution == Subgroup)
22982294
{
2299-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
2300-
{
2301-
Id = Id & (get_max_sub_group_size() - 1);
2302-
}
23032295
return __builtin_IB_simd_shuffle_df( Value, Id );
23042296
}
23052297
else
@@ -3229,10 +3221,6 @@ double SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffle, _i32_f64_i32, )(
32293221
{
32303222
if (Execution == Subgroup)
32313223
{
3232-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
3233-
{
3234-
c = c & (get_max_sub_group_size() - 1);
3235-
}
32363224
return __builtin_IB_simd_shuffle_df(x, c);
32373225
}
32383226
return 0;
@@ -3244,10 +3232,6 @@ half SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffle, _i32_f16_i32, )(in
32443232
{
32453233
if (Execution == Subgroup)
32463234
{
3247-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
3248-
{
3249-
c = c & (get_max_sub_group_size() - 1);
3250-
}
32513235
return __builtin_IB_simd_shuffle_h(x, c);
32523236
}
32533237
return 0;
@@ -3280,10 +3264,6 @@ char SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffleDown, _i32_i8_i32, )
32803264
{
32813265
if (Execution == Subgroup)
32823266
{
3283-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
3284-
{
3285-
c = c & (get_max_sub_group_size() - 1);
3286-
}
32873267
return __builtin_IB_simd_shuffle_down_uc(x, 0, c);
32883268
}
32893269
return 0;
@@ -3293,10 +3273,6 @@ short SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffleDown, _i32_i16_i32,
32933273
{
32943274
if (Execution == Subgroup)
32953275
{
3296-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
3297-
{
3298-
c = c & (get_max_sub_group_size() - 1);
3299-
}
33003276
return __builtin_IB_simd_shuffle_down_us(x, 0, c);
33013277
}
33023278
return 0;
@@ -3306,10 +3282,6 @@ int SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffleDown, _i32_i32_i32, )
33063282
{
33073283
if (Execution == Subgroup)
33083284
{
3309-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
3310-
{
3311-
c = c & (get_max_sub_group_size() - 1);
3312-
}
33133285
return __builtin_IB_simd_shuffle_down(x, 0, c);
33143286
}
33153287
return 0;
@@ -3319,10 +3291,6 @@ long SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffleDown, _i32_i64_i32,
33193291
{
33203292
if (Execution == Subgroup)
33213293
{
3322-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
3323-
{
3324-
c = c & (get_max_sub_group_size() - 1);
3325-
}
33263294
uint2 X = as_uint2(x);
33273295
uint2 result = (uint2)(__builtin_IB_simd_shuffle_down(X.s0, 0, c),
33283296
__builtin_IB_simd_shuffle_down(X.s1, 0, c));
@@ -3335,10 +3303,6 @@ float SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffleDown, _i32_f32_i32,
33353303
{
33363304
if (Execution == Subgroup)
33373305
{
3338-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
3339-
{
3340-
c = c & (get_max_sub_group_size() - 1);
3341-
}
33423306
return as_float(__builtin_IB_simd_shuffle_down(as_uint(x), 0, c));
33433307
}
33443308
return 0;
@@ -3349,10 +3313,6 @@ double SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffleDown, _i32_f64_i32
33493313
{
33503314
if (Execution == Subgroup)
33513315
{
3352-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
3353-
{
3354-
c = c & (get_max_sub_group_size() - 1);
3355-
}
33563316
uint2 X = as_uint2(x);
33573317
uint2 result = (uint2)(__builtin_IB_simd_shuffle_down(X.s0, 0, c),
33583318
__builtin_IB_simd_shuffle_down(X.s1, 0, c));
@@ -3367,10 +3327,6 @@ half SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffleDown, _i32_f16_i32,
33673327
{
33683328
if (Execution == Subgroup)
33693329
{
3370-
if(BIF_FLAG_CTRL_GET(UseOOBChecks))
3371-
{
3372-
c = c & (get_max_sub_group_size() - 1);
3373-
}
33743330
return as_half(__builtin_IB_simd_shuffle_down_us(as_ushort(x), 0, c));
33753331
}
33763332
return 0;
@@ -3383,10 +3339,6 @@ TYPE SPIRV_OVERLOADABLE SPIRV_BUILTIN(GroupNonUniformShuffleUp, _i32_##TYPE_ABBR
33833339
{ \
33843340
if (Execution == Subgroup) \
33853341
{ \
3386-
if(BIF_FLAG_CTRL_GET(UseOOBChecks)) \
3387-
{ \
3388-
c = c & (get_max_sub_group_size() - 1); \
3389-
} \
33903342
return intel_sub_group_shuffle_up((TYPE) 0, x, c); \
33913343
} \
33923344
return 0; \

‎IGC/Compiler/Builtins/BIFFlagCtrl/BIFFlagCtrlResolution.cpp‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,6 @@ void BIFFlagCtrlResolution::FillFlagCtrl() {
104104
BIF_FLAG_CTRL_SET(JointMatrixLoadStoreOpt, IGC_GET_FLAG_VALUE(JointMatrixLoadStoreOpt));
105105
}
106106

107-
BIF_FLAG_CTRL_SET(UseOOBChecks, PtrCGC->platform.needsOutOfBoundsBuiltinChecks());
108107
}
109108

110109
#undef BIF_FLAG_CTRL_SET

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